Abstract: There is provided an air conditioning system that can reduce a power consumption while maintaining constant temperature controlling capability. To this end, a water air conditioning system includes a heat source unit to cool water, a utilization heat exchanger to exchange heat between air and the water cooled by the heat source unit, a secondary pump to cause the water to flow in the utilization heat exchanger, a water temperature sensor to detect a temperature of the water cooled by the heat source unit, and airflow volume changing means to increase an airflow volume of the air passing through the utilization heat exchanger when the temperature of the water cooled by the heat source unit becomes higher.

Abstract: A method for detecting a position of a mobile body moving on a plane includes setting X-axis and Y-axis direction reference lines on the plane, disposing a dummy mobile body on intersection points of the reference lines, detecting a position of the dummy mobile body, determining position variation amounts at the intersection points as an X-axis direction error and a Y-axis direction error based on a difference from true position data, determining X-axis and Y-axis direction error approximate formulas based on the errors to calculate errors at each position on the reference lines, detecting the position of the mobile body, correcting acquired detected X-Y coordinate data by a linear interpolation method using the X-axis and Y-axis direction error approximate formulas, and obtaining position data close to the true position of the mobile body.

Abstract: A method for detecting a position of a mobile body moving on a plane includes setting X-axis and Y-axis direction reference lines on the plane, disposing a dummy mobile body on intersection points of the reference lines, detecting a position of the dummy mobile body, determining position variation amounts at the intersection points as an X-axis direction error and a Y-axis direction error based on a difference from true position data, determining X-axis and Y-axis direction error approximate formulas based on the errors to calculate errors at each position on the reference lines, detecting the position of the mobile body, correcting acquired detected X-Y coordinate data by a linear interpolation method using the X-axis and Y-axis direction error approximate formulas, and obtaining position data close to the true position of the mobile body.

Abstract: A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.

Abstract: A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.

Abstract: A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.

Abstract: A way to combine the metal bitline with the vertical interconnection to the capacitor over the bitline. In this class of embodiments, the vertical interconnect pillar is formed before fabrication of the bitline is completed. To accomplish this, the bitline metal is patterned using a step which allows it to extend vertically along the walls of the vertical interconnect pillar, but does not create any electrical connection between the bitline metal and the vertical interconnect pillar.

Abstract: A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.

Abstract: A way to combine the metal bitline with the vertical interconnection to the capacitor over the bitline. In this class of embodiments, the vertical interconnect pillar is formed before fabrication of the bitline is completed. To accomplish this, the bitline metal is patterned using a step which allows it to extend vertically along the walls of the vertical interconnect pillar, but does not create any electrical connection between the bitline metal and the vertical interconnect pillar.

Abstract: The invention relates to a method for forming connection holes reliably by making contact resistance low and uniform in semiconductor devices. Insulating layer 3, that includes SOG layer 7, is plasma etched using an etching gas with a small quantity of a gas with a low C/F ratio, such as CHF3, mixed with a gas with a high C/F ratio, such as C4F8/Ar/O2 at a ratio of 1:3.

Abstract: A method for fabricating DRAMs each having a COB structure, and the semiconductor device formed by this method, are provided. In one embodiment, the word line and/or bit line is covered with an insulating film having a comparatively small etching rate. Contact holes are formed while being defined by those insulating films in self-alignment.

Abstract: A semiconductor memory device has a semiconductor substrate, and memory cells provided at intersections between word line conductors and bit line conductors. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, and the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors.

Abstract: In an embodiment of a method of manufacturing semiconductor integrated circuit devices according to the present invention, word lines are provided in a straight form, which serve as gate electrodes of two selecting MOSFETs formed symmetrical about a center portion of an active region surrounded by a LOCOS oxide film on a semiconductor substrate, and bit lines have straight segments and protruding segments. Each protruding segment is formed to protrude from the bit line and is connected through a first contact hole to a first semiconductor region formed at the center portion of the active region. The straight line segments and the protruding segments are formed separately by two separate exposure steps.

Abstract: A phase shifting mask is used for manufacturing a semiconductor integrated circuit device including a conductor pattern in which the line width of patterned conductor strips or the space between patterned conductor strips is not constant. For main transparent areas in the mask corresponding to the conductor pattern, auxiliary pattern segments are provided for compensating changes in the phase distribution of transmitted light caused by changes of the line width or the space. Alternately, the spaces between the conductor strips are adjusted to suppress the changes in the phase distribution of transmitted light. Whether the auxiliary pattern segments should have the phase shifting function is determined depending upon the disposition of the main transparent areas.

Abstract: A semiconductor device, such as a dynamic RAM, and method of making it. A number of stacked cell capacitors are placed at a prescribed spacing in an alignment direction on top of a p.sup.- -type silicon substrate (1). Each capacitor has a nearly perpendicular cylindrical lower electrode (cylindrical polysilicon layer (96)), a dielectric film (silicon nitride film (77)), and upper electrode (plate electrode (78) made of polysilicon). The spacing in the alignment direction is smaller than the inner diameter of the lower electrode.

Abstract: A semiconductor memory device has a semiconductor substrate, word line conductors and bit line conductors, and memory cells provided at intersections between the word line conductors and bit line conductors. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors.

Abstract: The etch-back amount of a silicon oxide film of a memory array which is a higher altitude portion is increased when etching back and flattening the silicon oxide film by arranging a first-layer wiring on a BPSG film covering an upper electrode of an information-storing capacitative element only in a peripheral circuit but not arranging it in the memory array.Thus, a DRAM having a stacked capacitor structure is obtained such that the level difference between the memory array and peripheral circuit is decreased, and the formation of wiring and connection holes are easy.

Abstract: A DRAM has memory cells provided at crossing points between word line conductors and bit line conductors. Each memory cell has a cell selection transistor and an information storage capacitor arranged over the bit line conductors. Unit active regions are defined in a main surface of a semiconductor substrate by a field isolation pattern. The field isolation pattern has a controlled length of extension of bird's beaks so that channel formation regions in each unit active region has almost no stepped portion to provide the cell selection transistors with a stabilized threshold voltage.

Abstract: A memory device has a semiconductor substrate, and memory cells provided at intersections between word line conductors and bit line conductors. Each memory cell has a switching transistor and an information storage capacitor. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors.

Abstract: A cell analyzing apparatus which employs flow cytometry to obtain the concentration (the cell count per unit volume) of a specimen under examination is adapted to measure either the cell count of a control specimen the concentration of which is known or the length of time the control specimen is measured. The concentration of the specimen under examination is calculated based upon the cell count thereof obtained over a length of measurement time identical with the length of measurement time of the control specimen. Alternatively, the concentration of the specimen under examination is calculated based upon the length of measurement time thereof needed to obtain a cell count identical with that of the control specimen.