Abstract: An information processing apparatus includes a processor configured to accept feature information on a specification of a target circuit to be designed. The processor is configured to refer to first correspondence information in which a plurality of parameter values are associated with respective index values for each piece of feature information on specifications of respective circuits to be configured in an integrated circuit. The processor is configured to calculate, for each of a plurality of combinations of parameter values related to the accepted feature information, a sum of the index values associated with respective parameter values included in the relevant combination of parameter values. The processor is configured to select one or more combinations of parameter values from among the plurality of combinations of parameter values on basis of the calculated sums. The processor is configured to output the selected combinations of parameter values.

Abstract: A timing error analysis method includes, extracting, from error information, a design value related to a delay amount of a signal path and a feature that is an input when a machine learning model learns with the design value as an output, estimating a correct answer value of the design value from the feature and the machine learning model learning a relationship between the design value and the feature, comparing the design value with the correct answer value and storing a comparison result, generating a comparison result list including countermeasures for eliminating the timing error according to the comparison result, aggregating signal paths included in the comparison result list for each design block to generate an error list including information indicating the signal paths aggregated for each of the design blocks and the countermeasures, and outputting the error list.

Abstract: An information processing apparatus includes a memory, and a processor coupled to the memory and configured to classify paths into ranges which are divided in a predetermined range unit and related to a coordinate value, based on a first feature amount that includes the coordinate value of a path, classify the paths into classes, based on a result of classifying the paths into the ranges and a second feature amount that includes a number of registers of the path, extract the path that has a maximum number of logic stages in each of the classes, and generate a timing path learning model that outputs a maximum limit value of a number of logic stages of a target path according to the first feature amount of the target path, based on training data that includes the number of logic stages and the first feature amount of the extracted path.

Abstract: A recording medium recording a detour wiring check program, the processing includes: acquiring target feature information regarding a target path in a target circuit and target positional information indicating a position of each cell on the target path; using a storage storing size information regarding a size of a frame used to determine whether there is a possibility that a wiring which couples cells on a path in a circuit detours; determining whether each cell between transmission and reception cells in the target path is included in a frame, which has a size based on target size information corresponding to the target feature information; and outputting that there is the possibility that the wiring which couples each cells on the target path detours when it is determined that at least one cell among the cells between the transmission and reception cells is not included in the frame.

Abstract: An optimum stage number calculation method executed by a processor, the optimum stage number calculation method includes extracting information on a signal path between a transmission cell and a reception cell that transmits and receives a signal according to a clock from net information indicating a connection relationship between a plurality of cells arranged and wired in a field programmable gate array, estimating a cell total delay amount indicating a total delay amount of cells allowed to be included in one period of the clock in the signal path from input information including at least clock period information indicating a length of one period of the clock, calculating the number of stages of logic cells included in the signal path from the cell total delay amount, and outputting number-of-stages information indicating the calculated number of stages of the logic cells.

Abstract: An information processing apparatus includes a memory and a processor: where the memory stores first correspondence information in which, regarding each of regions delimited based on a level of possibility that a path included in a circuit does not meet timing constraints, region information representing the region and a range of a value of an item relating to delay of the path are associated with each other and second correspondence information in which, regarding a certain region, region information that represents the certain region and countermeasure information that represents a countermeasure against delay of the path whose value of the item corresponds to the certain region are associated with each other; and the processor outputs the countermeasure information by referring to the first and the second correspondence information, regarding a value of the item relating to delay of a path included in a target circuit of verification.

Abstract: An information processing apparatus for design assistance including: a memory storing first correspondence relationship information in which feature information of a circuit and a value to be set to a parameter for use to cause an integrated circuit capable of configuring the circuit therein to configure the circuit are associated with each other, and second correspondence relationship information in which each of multiple values settable to the parameter and an improvement level of a performance of the circuit configured by the integrated circuit with the value set to the parameter are associated with each other; and a processor receives feature information related of a target circuit to be designed; if a value of a parameter set to the integrated circuit to configure the target circuit satisfies a predetermined constraint, the received feature information and the value are stored and accumulated in the first correspondence relationship information.

Abstract: A timing error analysis method includes, extracting, from error information, a design value related to a delay amount of a signal path and a feature that is an input when a machine learning model learns with the design value as an output, estimating a correct answer value of the design value from the feature and the machine learning model learning a relationship between the design value and the feature, comparing the design value with the correct answer value and storing a comparison result, generating a comparison result list including countermeasures for eliminating the timing error according to the comparison result, aggregating signal paths included in the comparison result list for each design block to generate an error list including information indicating the signal paths aggregated for each of the design blocks and the countermeasures, and outputting the error list.

Abstract: An optimum stage number calculation method executed by a processor, the optimum stage number calculation method includes extracting information on a signal path between a transmission cell and a reception cell that transmits and receives a signal according to a clock from net information indicating a connection relationship between a plurality of cells arranged and wired in a field programmable gate array, estimating a cell total delay amount indicating a total delay amount of cells allowed to be included in one period of the clock in the signal path from input information including at least clock period information indicating a length of one period of the clock, calculating the number of stages of logic cells included in the signal path from the cell total delay amount, and outputting number-of-stages information indicating the calculated number of stages of the logic cells.

Abstract: A recording medium recording a detour wiring check program, the processing includes: acquiring target feature information regarding a target path in a target circuit and target positional information indicating a position of each cell on the target path; using a storage storing size information regarding a size of a frame used to determine whether there is a possibility that a wiring which couples cells on a path in a circuit detours; determining whether each cell between transmission and reception cells in the target path is included in a frame, which has a size based on target size information corresponding to the target feature information; and outputting that there is the possibility that the wiring which couples each cells on the target path detours when it is determined that at least one cell among the cells between the transmission and reception cells is not included in the frame.

Abstract: A method includes setting a first logical value in a control register provided in a variable delay control circuit that is included in a memory controller, detecting a first stuck-at fault of a second logical value that is a value except for the first logical value, the first stuck-at fault having occurred in one of a plurality of control lines, in accordance with a result of a comparison between a logical value output from the memory controller and an expected value of the logical value, setting the second logical value in the memory controller, and detecting a second stuck-at fault of the first logical value, the second stuck-at fault having occurred in one of the plurality of control lines, in accordance with a result of a comparison between a logical value output from the memory controller and an expected value of the logical value.

Abstract: An information processing apparatus includes a processor configured to accept feature information on a specification of a target circuit to be designed. The processor is configured to refer to first correspondence information in which a plurality of parameter values are associated with respective index values for each piece of feature information on specifications of respective circuits to be configured in an integrated circuit. The processor is configured to calculate, for each of a plurality of combinations of parameter values related to the accepted feature information, a sum of the index values associated with respective parameter values included in the relevant combination of parameter values. The processor is configured to select one or more combinations of parameter values from among the plurality of combinations of parameter values on basis of the calculated sums. The processor is configured to output the selected combinations of parameter values.

Abstract: An information processing apparatus includes a memory and a processor: where the memory stores first correspondence information in which, regarding each of regions delimited based on a level of possibility that a path included in a circuit does not meet timing constraints, region information representing the region and a range of a value of an item relating to delay of the path are associated with each other and second correspondence information in which, regarding a certain region, region information that represents the certain region and countermeasure information that represents a countermeasure against delay of the path whose value of the item corresponds to the certain region are associated with each other; and the processor outputs the countermeasure information by referring to the first and the second correspondence information, regarding a value of the item relating to delay of a path included in a target circuit of verification.

Abstract: An information processing apparatus for design assistance including: a memory storing first correspondence relationship information in which feature information of a circuit and a value to be set to a parameter for use to cause an integrated circuit capable of configuring the circuit therein to configure the circuit are associated with each other, and second correspondence relationship information in which each of multiple values settable to the parameter and an improvement level of a performance of the circuit configured by the integrated circuit with the value set to the parameter are associated with each other; and a processor receives feature information related of a target circuit to be designed; if a value of a parameter set to the integrated circuit to configure the target circuit satisfies a predetermined constraint, the received feature information and the value are stored and accumulated in the first correspondence relationship information.

Abstract: A memory controller has a first input buffer that determines a data signal that is to be received, on the basis of a reference voltage, a second inputs buffer that inputs a data strobe signal that is to be received, a data latch circuit that fetches an internal data signal, which is outputted by the first input buffer, on the basis of a phase of a rising edge and a falling edge of an internal data strobe signal, which is outputted by the second input buffer, a duty ratio detection circuit that detects a duty ratio of the internal data strobe signal, and a reference voltage generating circuit that adjusts the reference voltage on the basis of the duty ratio detected by the duty ratio detection circuit.

Abstract: A method includes setting a first logical value in a control resistor provided in a variable delay control circuit that is included in a memory controller, detecting a first stuck-at fault of a second logical value that is a value except for the first logical value, the first stuck-at fault having occurred in one of a plurality of control lines, in accordance with a result of a comparison between a logical value output from the memory controller and an expected value of the logical value, setting the second logical value in the memory controller, and detecting a second stuck-at fault of the first logical value, the second stuck-at fault having occurred in one of the plurality of control lines, in accordance with a result of a comparison between a logical value output from the memory controller and an expected value of the logical value.

Abstract: An EVEN component selecting unit and an ODD component selecting unit acquire a first signal from a DQ signal based on a rising edge of a DQS signal and a second signal from the DQ signal based on a falling edge of the DQS signal. Variable delay adding units give the first signal a first delay based on a phase difference between an internal clock signal and the rising edge of the DQS signal and give the second signal a second delay based on a phase difference between the internal clock signal and the falling edge of the DQS signal. Data capturing units capture, based on the internal clock signal, data from the first signal to which the first delay is given and the second signal to which the second delay is given.

Abstract: A signal control circuit includes: a delay acquisition circuit configured to obtain a first delay amount to be added to an input signal for aligning timing of rise of the input signal with timing of fall or rise of a reference signal and a second delay amount to be added to the input signal for aligning timing of fall of the input signal with timing of the fall or the rise of the reference signal; and a ratio calculation circuit configured to calculate a duty ratio of the input signal based on a difference between the first delay amount and the second delay amount.

Abstract: A memory controller has a first input buffer that determines a data signal that is to be received, on the basis of a reference voltage, a second inputs buffer that inputs a data strobe signal that is to be received, a data latch circuit that fetches an internal data signal, which is outputted by the first input buffer, on the basis of a phase of a rising edge and a falling edge of an internal data strobe signal, which is outputted by the second input buffer, a duty ratio detection circuit that detects a duty ratio of the internal data strobe signal, and a reference voltage generating circuit that adjusts the reference voltage on the basis of the duty ratio detected by the duty ratio detection circuit.

Abstract: An EVEN component selecting unit and an ODD component selecting unit acquire a first signal from a DQ signal based on a rising edge of a DQS signal and a second signal from the DQ signal based on a falling edge of the DQS signal. Variable delay adding units give the first signal a first delay based on a phase difference between an internal clock signal and the rising edge of the DQS signal and give the second signal a second delay based on a phase difference between the internal clock signal and the falling edge of the DQS signal. Data capturing units capture, based on the internal clock signal, data from the first signal to which the first delay is given and the second signal to which the second delay is given.