Abstract: Semiconductor device 3 comprises semiconductor chip 11, Au ball bumps 21 formed on pad electrodes 12 with a stud bump method, and thermoplastic adhesive layer 22 provided on the surface of semiconductor chip 11 on which pad electrodes 12 are formed, in which the tops of Au ball bumps 21 project from the surface of adhesive layer 22. Reliable bonding can be realized by forming the bumps for electrical connection and the adhesive resin having an adhesion function on the semiconductor chip. In addition, the present invention provides a method of bonding a copper foil to a semiconductor wafer to form a wiring pattern, a multi chip module in which electrical connection is established by bumps bonded to each other through an adhesive layer, and the like.

Abstract: The semiconductor package is highly reliable and has a construction that enables an improvement of fabrication yield and that can greatly reduce the number of steps and the amount of time required for those steps. The semiconductor package has a construction in which wiring layer 14 is supported by insulating film 13 over a range corresponding to chip electrodes 12 of semiconductor chip 11.

Abstract: Semiconductor device 3 comprises semiconductor chip 11, Au ball bumps 21 formed on pad electrodes 12 with a stud bump method, and thermoplastic adhesive layer 22 provided on the surface of semiconductor chip 11 on which pad electrodes 12 are formed, in which the tops of Au ball bumps 21 project from the surface of adhesive layer 22. Reliable bonding can be realized by forming the bumps for electrical connection and the adhesive resin having an adhesion function on the semiconductor chip. In addition, the present invention provides a method of bonding a copper foil to a semiconductor wafer to form a wiring pattern, a multi chip module in which electrical connection is established by bumps bonded to each other through an adhesive layer, and the like.

Abstract: A semiconductor package and fabrication method of the semiconductor package are provided. The semiconductor package is highly reliable and has a construction that enables an improvement of fabrication yield and that can greatly reduce the number of steps and the amount of time required for steps. The semiconductor package has a construction in which wiring layer 14 is supported by insulating film 13 over a range corresponding to chip electrodes 12 of semiconductor chip 11.

Abstract: The semiconductor package is highly reliable and has a construction that enables an improvement of fabrication yield and that can greatly reduce the number of steps and the amount of time required for those steps. The semiconductor package has a construction in which wiring layer 14 is supported by insulating film 13 over a range corresponding to chip electrodes 12 of semiconductor chip 11.

Abstract: Semiconductor device 3 comprises semiconductor chip 11, Au ball bumps 21 formed on pad electrodes 12 with a stud bump method, and thermoplastic adhesive layer 22 provided on the surface of semiconductor chip 11 on which pad electrodes 12 are formed, in which the tops of Au ball bumps 21 project from the surface of adhesive layer 22. Reliable bonding can be realized by forming the bumps for electrical connection and the adhesive resin having an adhesion function on the semiconductor chip. In addition, the present invention provides a method of bonding a copper foil to a semiconductor wafer to form a wiring pattern, a multi chip module in which electrical connection is established by bumps bonded to each other through an adhesive layer, and the like.

Abstract: A semiconductor package and fabrication method of the semiconductor package are provided. The semiconductor package is highly reliable and has a construction that enables an improvement of fabrication yield and that can greatly reduce the number of steps and the amount of time required for steps. The semiconductor package has a construction in which wiring layer 14 is supported by insulating film 13 over a range corresponding to chip electrodes 12 of semiconductor chip 11.

Abstract: A bonding tool for bonding an inner lead to an electrode pad of a semiconductor chip, wherein the bonding tool has a head surface which is rectangular. The rectangular head surface has a long side that is perpendicular to a longitudinal direction of the inner lead and wider than a width of the inner lead, and a short side that is narrower than an opening in a passivation film.

Abstract: A TAB tape is provided which has a ground layer which is connected to a ground wire within a device hole in a base film. A resin sealing hole for the purpose of holding in place a semiconductor chip and the base film is provided in the center of the ground layer, and a package in which a ground wire 8 is connected to a ground pad electrode is sealed with resin. Then, after forming bumps for heat radiating and grounding in the openings in the covering resist over the ground layer, the package is cut away, and is laid onto and joined to a printed circuit board, thereby forming shortened ground wiring within the semiconductor chip, not only reducing the inductance thereof, but also improving its radiation of heat.

Abstract: A transparent base film of a semiconductor device package has a device hole into which a semiconductor chip is inserted. Formed on the base film are a plurality of pads arranged as a matrix from wirings for connecting the plurality of pads to the electrodes of the semiconductor chip. A transparent cover resist is applied to the entire surface of the base film except for the top portions of the plurality of pads, and spherical bumps are formed respectively on the plurality of pads. With this arrangement, it is possible to make inspection of bonding conditions between the bumps and the outer lead bonding pads on a printed circuit board even after the package is mounted on the printed circuit board.

Abstract: The method for fabricating a semiconductor device disclosed is to bond an inner lead and a pad of a semiconductor chip together using a bonding tool. The bonding tool has a bottom peripheral end being formed in either a circular arc shape with a curvature or a sloped surface shape with a chamfer angle. The inner lead is placed over the pad of the semiconductor chip, and the bonding tool is placed at a location inside an edge of a passivation film formed at a peripheral portion of the pad. The inner lead and the pad of the semiconductor chip are pressed together by using the bonding tool. This enables the reliable bonding of the inner lead and the semiconductor chip pad without requiring to use a bump structure.

Abstract: A film carrier tape for use in TAB, having a lead wiring of a desired shape, and formed on a base film having a sprocket hole for conveyance and positioning, for connecting electrode pads of a semiconductor chip, includes a corner slit formed in at least one portion of four corner portions of a suspender positioned between a device hole and outer lead holes so as to vertically communicate.

Abstract: There is disclosed a single point TAB technology of sequentially bonding a number of inner leads to corresponding electrodes arranged along each edge of a rectangular principal surface of a semiconductor chip, one lead at a time.

Abstract: A bonding tool for connecting inner leads to pads of a semiconductor chip by means of high efficiency transmittance of ultrasonic vibrations is disclosed. The shape of the tool as seen in a plane parallel to the ultrasonic vibration is either to have a substantially flat plane on one side and a uniformly continuous sloped plane with a predetermined angle starting from a pressing face against the inner lead, or to have the shape of a uniformly continuous machined conical surface starting upwardly from the pressing face until the diameter of the cone reaches 200 .mu.m or more.

Abstract: Conductive leads are connected at inner ends thereof to electrodes of a semiconductor chip through a tape automated bonding process, and bumps are formed on the other ends of the conductive leads so as to economically and reliably mount the semiconductor chip on a circuit board through a concurrent reflow.

Abstract: A film carrier semiconductor device includes a film carrier tape, an outer lead bonding bump mounting portion, a semiconductor chip, inner lead bonding leads, and outer lead bonding bumps. The film carrier tape consists of a tape-like insulating material and has carrying and positioning sprocket holes in its both edge portions. The outer lead bonding bump mounting portion is formed in a central portion of the film carrier tape. The semiconductor chip is mounted on the outer lead bonding bump mounting portion and has electrode bumps formed on electrode pads. The inner lead bonding leads are formed into a predetermined pattern on the film carrier tape and connected to the electrode bumps. The outer lead bonding bumps are formed on the outer lead bonding bump mounting portion, to each of which one end of a corresponding one of the inner lead bonding leads is connected.