Patents by Inventor Mieko Suzuki
Mieko Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240074563Abstract: According to the present disclosure, makeup is put on based on the characteristics of the face of the person who is having the makeup put on. A control part and an application part are provided, where the control part includes: an area determining part configured to determine an area to apply a cosmetic product, based on a selected application pattern and at least two application characteristic points on a face; and a command part configured to command an application device to apply the cosmetic product to the area, and where the application part applies the cosmetic product to the area as commanded by the control part.Type: ApplicationFiled: September 30, 2020Publication date: March 7, 2024Inventors: Mieko NASU, Daisuke KAMIWANO, Maro TOKUSHIGE, Takahiro SUZUKI, Takashi MARUYAMA
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Patent number: 7167229Abstract: An active matrix drive type liquid crystal display element capable of preventing deterioration of display capability caused by a stripe domain, and a projection type display device using the liquid crystal display element, by which there is provided a projection type display device comprising a light source; a light convergence optical system for guiding a light emitted from said light source to a liquid crystal display element; and a projection optical system for enlarging and projecting a light subjected to light modulation by said liquid crystal display element; wherein the liquid crystal display element is configured by holding a liquid crystal layer between a pair of substrates arranged to face to each other, and a twisted nematic type liquid crystal material used in the liquid crystal layer satisfies dielectric constant anisotropy ?? of 0<??<8 and twist elasticity modulus K22 of K22>6.0 pN when the refractive index anisotropy ?n is 0.16??n?0.Type: GrantFiled: March 28, 2005Date of Patent: January 23, 2007Assignee: Sony CorporationInventors: Akiko Toriyama, Mieko Suzuki
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Patent number: 7123336Abstract: An active matrix drive type liquid crystal display element capable of preventing deterioration of display capability caused by a stripe domain, and a projection type display device using the liquid crystal display element, by which there is provided a projection type display device comprising a light source; a light convergence optical system for guiding a light emitted from said light source to a liquid crystal display element; and a projection optical system for enlarging and projecting a light subjected to light modulation by said liquid crystal display element; wherein the liquid crystal display element is configured by holding a liquid crystal layer between a pair of substrates arranged to face to each other, and a twisted nematic type liquid crystal material used in the liquid crystal layer satisfies dielectric constant anisotropy ?? of 0<??<8 and twist elasticity modulus K22 of K22>6.0 pN when the refractive index anisotropy ?n is 0.16??n?0.Type: GrantFiled: September 30, 2003Date of Patent: October 17, 2006Assignee: Sony CorporationInventors: Akiko Toriyama, Mieko Suzuki
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Patent number: 6951512Abstract: There is provided an apparatus for polishing a substrate, including (a) a polishing pad formed with a plurality of through-holes through which polishing material is supplied to a surface of the polishing pad, (b) a level block on which the polishing pad is mounted, and (c) a rotatable carrier for supporting a substrate thereon, the carrier being positioned in facing relation with the level block, the level block being rotatable around a rotation axis thereof with the rotation axis being moved along an arcuate path, and causing the polishing pad to make contact with the substrate for polishing the substrate, the polishing pad having a first ring-shaped region concentric thereto where no through-holes are formed. For instance, the first ring-shaped region has a width greater than 10%, but smaller than 95% of a radius of the polishing pad. The apparatus enhances uniformity in polishing a substrate.Type: GrantFiled: July 22, 2004Date of Patent: October 4, 2005Assignee: NEC Electronics CorporationInventors: Mieko Suzuki, Yasuaki Tsuchiya
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Publication number: 20050185132Abstract: An active matrix drive type liquid crystal display element capable of preventing deterioration of display capability caused by a stripe domain, and a projection type display device using the liquid crystal display element, by which there is provided a projection type display device comprising a light source; a light convergence optical system for guiding a light emitted from said light source to a liquid crystal display element; and a projection optical system for enlarging and projecting a light subjected to light modulation by said liquid crystal display element; wherein the liquid crystal display element is configured by holding a liquid crystal layer between a pair of substrates arranged to face to each other, and a twisted nematic type liquid crystal material used in the liquid crystal layer satisfies dielectric constant anisotropy ?? of 0<??<8 and twist elasticity modulus K22 of K22>6.0 pN when the refractive index anisotropy ?n is 0.16??n?0.Type: ApplicationFiled: March 28, 2005Publication date: August 25, 2005Inventors: Akiko Toriyama, Mieko Suzuki
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Publication number: 20050024578Abstract: An active matrix drive type liquid crystal display element capable of preventing deterioration of display capability caused by a stripe domain, and a projection type display device using the liquid crystal display element, by which there is provided a projection type display device comprising a light source; a light convergence optical system for guiding a light emitted from said light source to a liquid crystal display element; and a projection optical system for enlarging and projecting a light subjected to light modulation by said liquid crystal display element; wherein the liquid crystal display element is configured by holding a liquid crystal layer between a pair of substrates arranged to face to each other, and a twisted nematic type liquid crystal material used in the liquid crystal layer satisfies dielectric constant anisotropy ?? of 0<??<8 and twist elasticity modulus K22 of K22>6.0 pN when the refractive index anisotropy ?n is 0.16??n?0.Type: ApplicationFiled: September 30, 2003Publication date: February 3, 2005Inventors: Akiko Toriyama, Mieko Suzuki
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Publication number: 20040259482Abstract: There is provided an apparatus for polishing a substrate, including (a) a polishing pad formed with a plurality of through-holes through which polishing material is supplied to a surface of the polishing pad, (b) a level block on which the polishing pad is mounted, and (c) a rotatable carrier for supporting a substrate thereon, the carrier being positioned in facing relation with the level block, the level block being rotatable around a rotation axis thereof with the rotation axis being moved along an arcuate path, and causing the polishing pad to make contact with the substrate for polishing the substrate, the polishing pad having a first ring-shaped region concentric thereto where no through-holes are formed. For instance, the first ring-shaped region has a width greater than 10%, but smaller than 95% of a radius of the polishing pad. The apparatus enhances uniformity in polishing a substrate.Type: ApplicationFiled: July 22, 2004Publication date: December 23, 2004Inventors: Mieko Suzuki, Yasuaki Tsuchiya
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Patent number: 6783446Abstract: There is provided an apparatus for polishing a substrate, including (a) a polishing pad formed with a plurality of through-holes through which polishing material is supplied to a surface of the polishing pad, (b) a level block on which the polishing pad is mounted, and (c) a rotatable carrier for supporting a substrate thereon, the carrier being positioned in facing relation with the level block, the level block being rotatable around a rotation axis thereof with the rotation axis being moved along an arcuate path, and causing the polishing pad to make contact with the substrate for polishing the substrate, the polishing pad having a first ring-shaped region concentric thereto where no through-holes are formed. For instance, the first ring-shaped region has a width greater than 10%, but smaller than 95% of a radius of the polishing pad. The apparatus enhances uniformity in polishing a substrate.Type: GrantFiled: February 24, 1999Date of Patent: August 31, 2004Assignee: NEC Electronics CorporationInventors: Mieko Suzuki, Yasuaki Tsuchiya
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Patent number: 6551914Abstract: A semiconductor device in which an interconnection material is buried in a hole formed in an interlevel insulating film arranged on a semiconductor substrate includes a protective layer formed on the surface of the interlevel insulating film that has a lower polishing rate than that of the interconnection material in chemical mechanical polishing. A method of manufacturing this semiconductor device is also disclosed.Type: GrantFiled: August 8, 2000Date of Patent: April 22, 2003Assignee: NEC Electronics CorporationInventors: Mieko Suzuki, Akira Kubo
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Patent number: 6361708Abstract: A method and an apparatus for polishing a metal film formed on a semiconductor device are disclosed. A semiconductor wafer is immersed in an oxidizing solution before it is polished. As a result, the undesirable part of a W film deposited on the circumferential edge of the wafer is removed by etching.Type: GrantFiled: May 14, 1998Date of Patent: March 26, 2002Assignee: NEC CorporationInventors: Akira Kubo, Mieko Suzuki
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Patent number: 6235071Abstract: The present invention provides a chemical mechanical polishing method for polishing a soft metal by supplying a polishing surface of the soft metal with a novel polishing slurry which includes at least both alumina particles as polishing particles and hydrogen peroxide as oxidizing agent, wherein the content of the alumina particles is in the range of 2-10% by weight of the total amount of the polishing slurry.Type: GrantFiled: February 26, 1999Date of Patent: May 22, 2001Assignee: NEC CorporationInventors: Yasuaki Tsuchiya, Mieko Suzuki
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Patent number: 6110014Abstract: A wafer polishing apparatus includes a carrier and a table. A wafer is mounted on the carrier, and the carrier includes a circumference ring provided around of the wafer. The height of the innermost portion of the circumference ring is equal to or higher than that of a surface of the wafer. The table includes a polishing pad. The carrier and the table are relatively rotated such that the wafer surface is polished by the polishing pad.Type: GrantFiled: November 17, 1998Date of Patent: August 29, 2000Assignee: NEC CorporationInventor: Mieko Suzuki
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Patent number: 6054383Abstract: A fabrication method of a semiconductor device is provided, which enables the formation of a conductive plug in an opening of an interlevel dielectric layer without arising any void. After a first wiring layer is formed on a first interlevel electric layer, a second interlevel dielectric layer is formed on the first interlevel dielectric layer to cover the first wiring layer. A first opening is formed in the second interlevel dielectric layer. A first conductive layer is formed on or over the second interlevel dielectric layer to cover the first opening. A first protection layer is formed on the first conductive layer to cover a first depressed part of the first conductive layer. The first protection layer having a first buried part on the first depressed part. The first protection layer and the first conductive layer are polished by a CMP process until the second interlevel dielectric layer is exposed, thereby selectively leaving the first depressed part within the first opening.Type: GrantFiled: November 21, 1996Date of Patent: April 25, 2000Assignee: NEC CorporationInventors: Mieko Suzuki, Tetsuya Homma
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Patent number: 5904558Abstract: A semiconductor device is formed with an interlayer insulation layer having its high flatness. A metal wiring is formed on a silicon substrate via a silicon oxide layer. A multi-layer silicon oxide layer that is to be the interlayer insulation film is formed over the insulation layer and the metal wiring. The multi-layer silicon layer consists of an upper most first silicon oxide layer, a lower most third silicon oxide layer and an intermediate second silicon oxide layer. The second silicon oxide layer has higher polishing rate than the first and third silicon oxide layer. By performing chemical mechanical polishing for the multilayer silicon oxide layer, a step formed by the presence of the metal layer can be satisfactorily eliminated fox planarizing the surface of the interlayer insulation film.Type: GrantFiled: February 13, 1997Date of Patent: May 18, 1999Assignee: NEC CorporationInventor: Mieko Suzuki
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Patent number: 5607880Abstract: The invention provides a fabrication method of multilevel interconnections for semiconductor integrated circuits. Aluminium wiring lines are formed on a first silicon oxide film overlying a silicon substrate. A second silicon oxide film is grown by a plasma chemical vapor deposition on the wiring lines and the first silicon oxide film for a specific surface treatment of either an etching with use of fluorine compounds or an ion-implantation of fluorine compounds. A third silicon oxide film is grown on the second silicon oxide film by an atmospheric pressure chemical vapor deposition with use of organic silicon compounds and an oxygen including ozone.Type: GrantFiled: April 28, 1993Date of Patent: March 4, 1997Assignee: NEC CorporationInventors: Mieko Suzuki, Tetsuya Homma
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Patent number: 5491108Abstract: A method which can markedly improve the flatness of a semiconductor integrated circuit device by forming selectively a layer insulating film on an underlying substrate having level differences is disclosed. First, a Ti--W alloy film is formed on a member which brings about level differences due to wirings or the like, then a PECVD silicon oxide film is formed followed by a plasma treatment using CF.sub.4 gas. Further, a silicon oxide film is deposited by atmospheric pressure CVD using ozone and tetraethoxysilane. Then, the surface is flattened by etchback using an organic SOG film, and a silicon oxide film is formed by plasma excited CVD.Type: GrantFiled: December 10, 1993Date of Patent: February 13, 1996Assignee: NEC CorporationInventors: Mieko Suzuki, Tetsuya Homma, Yukinobu Murao, Takaho Tanigawa, Hiroki Koga
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Patent number: 5420075Abstract: A method of manufacturing a semiconductor device, incorporates the steps of: performing reactive ion etching using a fluorine compound gas to surface-treat the lower level wirings which permits selective deposition of the second silicon oxide film; selectively depositing a second silicon oxide film between said lower level wirings by a CVD method using an organic silicon compound gas and an oxidizable gas as source gases; depositing a third silicon oxide film on an entire surface and forming through holes connected to the lower wirings; and forming upper level wirings connected to the lower level wirings. Further, an additional silicon oxide film can be deposited on the major surface so as to form a side wall thereof on the lower level wirings. The reactive ion etching is then performed.Type: GrantFiled: April 14, 1993Date of Patent: May 30, 1995Assignee: NEC CorporationInventors: Tetsuya Homma, Mieko Suzuki
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Patent number: 5332694Abstract: A process for manufactoring a semiconductor device having a double- or multi-level interconnection structure is disclosed. The process includes steps of: forming a first level metal interconnect; then forming a first silicon oxide layer by PECVD, and forming a second silicon oxide layer by atmospheric CVD using tetraethoxysilane and oxygen containing ozone under a condition of excess ozone in which the ratio of flow-rate of ozone to flow-rate of tetraethoxysilane is about 20:1. An organic compound coating layer is formed by spin-coating accompanied by a thermal treatment. The organic compound coating layer and the second silicon oxide layer are etched-back to remove the compound oxide layer completely. A third silicon oxide layer is formed by PECVD; and forming a second level metal interconnect. A good planarization can be obtained and a failure, such as delamination or blister due to bumping, of the third silicon oxide layer can be avoided.Type: GrantFiled: February 23, 1993Date of Patent: July 26, 1994Assignee: NEC CorporationInventor: Mieko Suzuki
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Patent number: 4552633Abstract: A fine particulate carrier for use in clinical testing which has a size of 0.5 to 20 microns and a process for producing thereof are herein disclosed.Type: GrantFiled: September 22, 1983Date of Patent: November 12, 1985Assignees: Japan Atomic Energy Research Institute, Japan Immunoresearch Laboratories Co., Ltd.Inventors: Minoru Kumakura, Isao Kaetsu, Mieko Suzuki, Masakazu Adachi