Abstract: A temperature-controlled showerhead assembly is configured to deliver a plurality of gases into a cyclic deposition chamber. The showerhead assembly comprises a showerhead body having a cavity formed therethrough and at a central region thereof, wherein the cavity is configured to diffuse or mix the gases prior to introducing the gases into the deposition chamber. The showerhead assembly additionally comprises a network of cooling channels configured to conduct heat away from the showerhead body. The showerhead assembly further comprises a network of heating elements configured to supply heat to the showerhead body, wherein the network of heating elements is disposed closer to the an upper surface of the showerhead body relative to the cooling channels.

Abstract: The disclosed technology relates generally to semiconductor processing and more particularly to liquid precursor injection apparatus and methods for depositing thin films. A method of injecting a liquid precursor into a thin film deposition chamber comprises delivering a vaporized liquid precursor into the thin film deposition chamber by atomizing the liquid precursor into atomized precursor droplets using a liquid injection unit and vaporizing the atomized precursor droplets into the vaporized liquid precursor in a vaporization chamber.

Abstract: The disclosed technology relates generally to semiconductor processing and more particularly to liquid precursor injection apparatus and methods for depositing thin films. A method of injecting a liquid precursor into a thin film deposition chamber comprises delivering a vaporized liquid precursor into the thin film deposition chamber by atomizing the liquid precursor into atomized precursor droplets using a liquid injection unit and vaporizing the atomized precursor droplets into the vaporized liquid precursor in a vaporization chamber.

Abstract: The disclosed technology relates generally to semiconductor manufacturing, and more particularly to precursor delivery in cyclic deposition. In one aspect, a thin film deposition system comprises a thin film deposition chamber configured to deposit a thin film by alternatingly exposing a substrate to a plurality of precursors. The thin film system additionally comprises a precursor source connected to the thin film deposition chamber by a precursor delivery line, wherein the precursor delivery line comprises a high conductance line portion between the precursor source and a final valve outside of the thin film deposition chamber. The high conductance line portion is elongated in a flow direction and has a conductance that is at least four times greater than either of immediately adjacent low conductance line portions connected at opposing ends of the high conductance line portion.

Abstract: The disclosed technology relates generally to semiconductor manufacturing, and more particularly to precursor delivery in cyclic deposition. In one aspect, a method of depositing a thin film comprises alternatingly exposing a substrate in a thin film deposition chamber to a plurality of precursors. Exposing the substrate comprises introducing one of the precursors into the thin film deposition chamber through two or more atomic layer deposition (ALD) valves each configured to supply the one of the precursors.

Abstract: The disclosed technology relates generally to semiconductor processing and more particularly to liquid precursor injection apparatus and methods for depositing thin films. A method of injecting a liquid precursor into a thin film deposition chamber comprises delivering a vaporized liquid precursor into the thin film deposition chamber by atomizing the liquid precursor into atomized precursor droplets using a liquid injection unit and vaporizing the atomized precursor droplets into the vaporized liquid precursor in a vaporization chamber.

Abstract: A chemical vapor deposition system is disclosed herein. The chemical vapor deposition system has a plurality of reaction chambers to operate independently in the growth of epitaxial layers on wafers within each of the reaction chambers for the purpose of reducing processing time while maintaining the quality necessary for the fabrication of high-performance semiconductor devices.

Abstract: An edge ring assembly used in a plasma etching chamber includes a dielectric coupling ring and a conductive edge ring. In one embodiment, the dielectric coupling ring has an annular projection extending axially upward from its inner periphery. The dielectric coupling ring is adapted to surround a substrate support in a plasma etching chamber. The conductive edge ring is adapted to surround the annular projection of the dielectric coupling ring. A substrate supported on the substrate support overhangs the substrate support and overlies the annular projection of the dielectric coupling ring and a portion of the conductive edge ring. In another embodiment, the dielectric coupling ring has a rectangular cross section. The dielectric coupling ring and the conductive edge ring are adapted to surround a substrate support in a plasma etching chamber. A substrate supported on the substrate support overhangs the substrate support and overlies a portion of the conductive edge ring.

Abstract: An edge ring assembly used in a plasma etching chamber includes a dielectric coupling ring and a conductive edge ring. In one embodiment, the dielectric coupling ring has an annular projection extending axially upward from its inner periphery. The dielectric coupling ring is adapted to surround a substrate support in a plasma etching chamber. The conductive edge ring is adapted to surround the annular projection of the dielectric coupling ring. A substrate supported on the substrate support overhangs the substrate support and overlies the annular projection of the dielectric coupling ring and a portion of the conductive edge ring. In another embodiment, the dielectric coupling ring has a rectangular cross section. The dielectric coupling ring and the conductive edge ring are adapted to surround a substrate support in a plasma etching chamber. A substrate supported on the substrate support overhangs the substrate support and overlies a portion of the conductive edge ring.

Abstract: An apparatus to supply a plurality of process fluids for processing a substrate in a semiconductor processing chamber. The apparatus includes a plurality of process fluid supply valves and a fluid supply network that is defined between a crossover valve and a tuning supply valve. The apparatus further includes a tuning fluid supply being connected to the fluid supply network through the tuning supply valve. Further included with the apparatus is a plurality of process fluids that are connected to the fluid supply network through the plurality of process fluid supply valves. A process chamber that has a substrate support is also included in the apparatus. The process chamber further including an edge fluid supply and a center fluid supply, the edge fluid supply connected to the fluid supply network through an edge enable valve and the center supply connected to the fluid supply network through a center enable valve.

Abstract: An apparatus to supply a plurality of process fluids for processing a substrate in a semiconductor processing chamber. The apparatus includes a plurality of process fluid supply valves and a fluid supply network that is defined between a crossover valve and a tuning supply valve. The apparatus further includes a tuning fluid supply being connected to the fluid supply network through the tuning supply valve. Further included with the apparatus is a plurality of process fluids that are connected to the fluid supply network through the plurality of process fluid supply valves. A process chamber that has a substrate support is also included in the apparatus. The process chamber further including an edge fluid supply and a center fluid supply, the edge fluid supply connected to the fluid supply network through an edge enable valve and the center supply connected to the fluid supply network through a center enable valve.

Abstract: An apparatus to supply a plurality of process fluids for processing a substrate in a semiconductor processing chamber is disclosed. The apparatus includes a plurality of process fluid supply valves and a fluid supply network that is defined between a crossover valve and a tuning supply valve. The apparatus further includes a tuning fluid supply being connected to the fluid supply network through the tuning supply valve. Further included with the apparatus is a plurality of process fluids that are connected to the fluid supply network through the plurality of process fluid supply valves. A process chamber that has a substrate support is also included in the apparatus. The process chamber further including an edge fluid supply and a center fluid supply, the edge fluid supply connected to the fluid supply network through an edge enable valve and the center supply connected to the fluid supply network through a center enable valve.

Abstract: An apparatus to supply a plurality of process fluids for processing a substrate in a semiconductor processing chamber is disclosed. The apparatus includes a plurality of process fluid supply valves and a fluid supply network that is defined between a crossover valve and a tuning supply valve. The apparatus further includes a tuning fluid supply being connected to the fluid supply network through the tuning supply valve. Further included with the apparatus is a plurality of process fluids that are connected to the fluid supply network through the plurality of process fluid supply valves. A process chamber that has a substrate support is also included in the apparatus. The process chamber further including an edge fluid supply and a center fluid supply, the edge fluid supply connected to the fluid supply network through an edge enable valve and the center supply connected to the fluid supply network through a center enable valve.

Abstract: CMP systems and methods implement instructions for moving a polishing pad relative to a wafer and a retainer ring and for applying pressure for CMP operations. Feedback of polishing pad position is coordinated with determinations of desired inputs of variable forces by which changing areas of the wafer, a pad conditioning puck, and the retainer ring are separately urged into contact with the polishing pad so that the pressure on each such area is separately controlled. Processing workload is evaluated according to criteria related to the characteristics of the instructions. If none of the criteria is exceeded, a central CMP processor is used for the processing. If any of the criteria is exceeded, the force determinations are made separately from the central CMP processor by a force controller, and the central processor manages data transfer to the force controller.

Abstract: A method and apparatus is disclosed for polishing a semiconductor wafer. A polishing pad including a first surface and a semiconductor wafer including a second surface are aligned to each other. To allow alignment of an axis of rotation of the surfaces, at least one of the first and second surfaces includes an adjustable axis of rotation. After the axis of rotation of the first and second surfaces is aligned, the adjustable axis of rotation is set, preferably with a magneto-rheological fluid or similarly acting material, to maintain a fixed position. Thereafter, the polishing pad is utilized to polish the semiconductor wafer.

Abstract: A platen is provided for use in a chemical mechanical planarization (CMP) system. The platen is provided with diaphragms that overcome a fluid-conservation problem experienced in prior air-bearing platens. The diaphragms enable a removal profile to be manipulated by configuring one or more diaphragms to control localized polishing pressure while capturing free-flowing fluid that is input to the apparatus. The diaphragms also minimize loss of normally-free-flowing fluid from a fluid-bearing.

Abstract: A temperature control device for controlling temperature of an upper chamber of a plasma processing apparatus is described. The temperature control device includes a thermally conductive body having an inner surface and an outer surface removably connected with and in thermal communication with the upper chamber of the plasma processing apparatus. The temperature control device also includes a plurality of thermal interface layers in thermal communication with the thermally conductive body wherein at least one layer is a heating element; and a cooling element connected with the banded thermally conductive body and thermally coupled with the upper chamber of the plasma processing apparatus wherein the cooling element is configured to conduct a fluidic medium.

Abstract: A chemical mechanical polishing (CMP) apparatus is provided. The CMP apparatus includes a first roller situated at a first point and a second roller situated at a second point. The first point is separate from the second point. Also included in the apparatus is a polishing pad strip having a first end secured to the first roller and a second end secured to the second roller. The first roller and the second roller are configured to reciprocate so that the polishing pad strip oscillates at least partially between the first point and the second point.

Abstract: Mating faces of a microchannel plate (MCP) (50) and a multi-layer ceramic body (80) unit are deposited with a thin film having protuberances (84) using a suitable metal selected for optimum diffusion at a desired temperatures and pressure. The metallized MCP (50) and multi-layer ceramic body (80) unit are then aligned and placed in a bonding fixture (F) that provides the necessary force applied to the components to initiate a diffusion bond at a desired elevated temperature. The bonding fixture (F) is then placed in a vacuum heat chamber (V) to accelerate the diffusion bonding process between the MCP (50) and the multi-layer ceramic body unit (80).

Abstract: CMP systems and methods provide necessary vacuum and pressure to be applied from a vacuum chuck through a carrier film to a wafer without interfering with desired wafer planarization during CMP operations. Prior low polish rate-areas on the wafer may be eliminated from an exposed surface of the wafer by structure to uniformly compress the carrier film in response to a force from the wafer on the carrier film during the CMP operations. A distance between, and diameters of, adjacent holes of the carrier film are reduced, and the locations of the holes are in an array to coordinate with passageways through the vacuum chuck. The structure significantly reduces a maximum value of compression of the carrier film during CMP operations. As a result, during the CMP operations the wafer does not deform in a manner that exactly matches the compression of the carrier film, but remains essentially flat.