Abstract: A method and apparatus for frame synchronization in digital communication systems using multiple modulation formats, including the Differential Phase Shift Keying (DPSK), Duobinary Signaling (DBS), and ON/OFF Keying (OOK) modulation formats, perform a search for both a frame alignment sequence (FAS) and the inverted FAS and determine the polarity of the received digital stream.

Abstract: The invention comprises a method and apparatus for adapting plesiochronous hierarchical layered data to produce synchronous hierarchical layered data. Similarly, the invention comprises a method and apparatus for adapting synchronous hierarchical layered data to produce plesiochronous hierarchical layered data.

Abstract: A method and apparatus are provided for transmitting and receiving a plurality of individual tributary signals in multiplex form via a common line. At the transmitting end, the tributary signals, each of which has a similar initial frequency, are converted into a compound signal having a frame structure with a common data rate. At the receiving end, each individual tributary signal is retrieved from the compound signal with its initial frequency. A phase information signal portion including a respective phase difference between each tributary signal and the compound signal is formed and inserted into the compound signal in the shape of respective coded bits. The initial frequency of each tributary signal is recovered from the phase information signal portion included in the respective coded bits belonging to the respective tributary signals.

Abstract: A method and apparatus for frame synchronization in digital communication systems using multiple modulation formats, including the Differential Phase Shift Keying (DPSK), Duobinary Signaling (DBS), and ON/OFF Keying (OOK) modulation formats, perform a search for both a frame alignment sequence (FAS) and the inverted FAS and determine the polarity of the received digital stream.

Abstract: The invention comprises a method and apparatus for adapting plesiochronous hierarchical layered data to produce synchronous hierarchical layered data. Similarly, the invention comprises a method and apparatus for adapting synchronous hierarchical layered data to produce plesiochronous hierarchical layered data.

Abstract: The invention relates to a data transmission system for the frame-oriented digital data transmission of a plurality of useful signals embedded in a carrier signal, using time-division multiplex operation, rate matching being undertaken between the useful signals and the carrier signal by means of stuff locations. The data to be stuffed, and the management information for the reassignment are embedded in previously unused 8 bytes in the path layer overhead of the carrier signal superframe, and protected by an HC(6,3,3) code. Clear channel signals can advantageously be transmitted using the system, and the transmission is time-transparent and data-transparent.

Abstract: A method and apparatus are provided for transmitting and receiving a plurality of individual tributary signals in multiplex form via a common line. At the transmitting end, the tributary signals, each of which has a similar initial frequency, are converted into a compound signal having a frame structure with a common data rate. At the receiving end, each individual tributary signal is retrieved from the compound signal with its initial frequency. A phase information signal portion including a respective phase difference between each tributary signal and the compound signal is formed and inserted into the compound signal in the shape of respective coded bits. The initial frequency of each tributary signal is recovered from the phase information signal portion included in the respective coded bits belonging to the respective tributary signals.

Abstract: The invention relates to a data transmission system and a method, in general, and to a data transmission system and a method for frame-oriented digital data, in particular.

Abstract: The invention relates to a data transmission system for the frame-oriented digital data transmission of a plurality of useful signals embedded in a carrier signal, using time-division multiplex operation, rate matching being undertaken between the useful signals and the carrier signal by means of stuff locations. The data to be stuffed, and the management information for the reassignment are embedded in previously unused 8 bytes in the path layer overhead of the carrier signal superframe, and protected by an HC(6,3,3) code. Clear channel signals can advantageously be transmitted using the system, and the transmission is time-transparent and data-transparent.

Abstract: A circuit for adjusting the bit rates of two signals is necessary for plesiochronous multiplexers, for example, to bring the plesiochronous signals, which are to be combined to one digital signal of the next higher hierarchy, to the same bit rate. For this purpose, the circuit arrangement comprises an elastic store (4) as well as a justification decision circuit (15, 16). In order that a circuit having such features can be used for bit rates of the order of 140 Mbit/s and yet can be arranged largely in CMOS technology, the bit clocks of the first and second signals are reduced at the ratio of 1:n. Furthermore, a serial-to-parallel converter (2) converts bit groups of n serial bits of a first signal into bit groups of n parallel bits, which are written in groups into the elastic store (4) and are also read out in groups. The parallel bit groups read out are applied to a controllable selection matrix (5) having n outputs, which transmits n selected bits of more than one bit group to n outputs.

Abstract: The described circuit arrangement for removing stuff bits from a frame-structured signal which is available in n parallel bits, comprises a memory circuit (2) which is supplied with the parallel bits (1b). The memory circuit (2) is followed by a controllable selection circuit (3) having n outputs (3a). A control circuit (9) produces control signals (9b, 9c), which determine which bits stored in the memory circuit are transported to the n outputs (3a) of the selection circuit (3). The memory circuit (2) comprises only n delay elements by which each of the n parallel bits (1b) is delayed for the duration of one bit. So as to provide that n delay elements will be sufficient, the control circuit (9) is to block at predetermined time intervals the acceptance of new bits in one or a plurality of delay elements.