Abstract: A method and system for a non-volatile memory (NVM) with multiple bits error correction are provided and may include detecting bit errors in a memory element, of a NVM array integrated within a chip, which remain uncorrected after forward error correction. A redundant memory element may be utilized when the errors may be detected utilizing a cyclic redundancy check, may be within the NVM array, and may include secure information. Access to the secure information and/or the chip may be disabled when the errors are detected. The FEC operation may include one or both of an error location operation and a correction operation. The errors may be corrected when a location may be known to include the errors. The NVM array may be partitioned into regions. At least one of the redundant memory elements may be substituted in place of the memory element based on a substitution priority.

Abstract: A method and system for a non-volatile memory (NVM) with multiple bits error correction are provided and may include detecting bit errors in a memory element, of a NVM array integrated within a chip, which remain uncorrected after forward error correction. A redundant memory element may be utilized when the errors may be detected utilizing a cyclic redundancy check, may be within the NVM array, and may include secure information. Access to the secure information and/or the chip may be disabled when the errors are detected. The FEC operation may include one or both of an error location operation and a correction operation. The errors may be corrected when a location may be known to include the errors. The NVM array may be partitioned into regions. At least one of the redundant memory elements may be substituted in place of the memory element based on a substitution priority.

Abstract: A method and system for a non-volatile memory (NVM) with multiple bits error correction and detection for improving production yield are provided. Forward error correction (FEC) operations and cyclic redundancy check (CRC) operations may be utilized in an NVM array integrated in a chip to correct errors in memory elements and detect remaining errors respectively. When remaining errors are detected, the memory element may be substituted by redundant memory elements in the NVM array. An erasure operation in the FEC may be utilized to correct errors when the error location is known. The NVM array may be partitioned into classes that may each have specified FEC operations and a specified priority to substitute memory elements by redundant memory elements. The FEC and CRC operations may be utilized to protect secure information stored in the NVM array by disabling the chip when errors are detected while reading the secure information.

Abstract: Certain aspects of a method and system for using multiple memory regions for redundant remapping are disclosed. Aspects of one method may include dividing at least a portion of on-chip memory into a plurality of memory regions. Each of the plurality of memory regions may be mapped into a corresponding plurality of redundant memory regions, wherein if an error is detected in at least one of the plurality of memory regions, at least one of the plurality of memory regions having the detected error may be remapped to at least one of the corresponding plurality of redundant memory regions.

Abstract: A method and system for a non-volatile memory (NVM) with multiple bits error correction and detection for improving production yield are provided. Forward error correction (FEC) operations and cyclic redundancy check (CRC) operations may be utilized in an NVM array integrated in a chip to correct errors in memory elements and detect remaining errors respectively. When remaining errors are detected, the memory element may be substituted by redundant memory elements in the NVM array. An erasure operation in the FEC may be utilized to correct errors when the error location is known. The NVM array may be partitioned into classes that may each have specified FEC operations and a specified priority to substitute memory elements by redundant memory elements. The FEC and CRC operations may be utilized to protect secure information stored in the NVM array by disabling the chip when errors are detected while reading the secure information.