Abstract: Systems and methods for identifying associations between a code snippet query and stored computer code stored. The method can receive a code query identifying a code snippet to search for, determine a fingerprint of the query code snippet, and search the stored software using the fingerprint to identify software results of code similar to the query code snippet. The fingerprint can be determined by generating k-grams of the code snippet. The k-grams used for the search can be down-selected based on a winnowing process. The method can remove from the software results code that is associated with sanctioned software. The method can include coalescing the software results to produce a subset of the software results, generating a code search user interface comprising information indicative of the subset of software results, and causing presentation of the code search user interface and displaying the subset of software results.

Abstract: Systems and methods for identifying associations between a code snippet query and stored computer code stored. The method can receive a code query identifying a code snippet to search for, determine a fingerprint of the query code snippet, and search the stored software using the fingerprint to identify software results of code similar to the query code snippet. The fingerprint can be determined by generating k-grams of the code snippet. The k-grams used for the search can be down-selected based on a winnowing process. The method can remove from the software results code that is associated with sanctioned software. The method can include coalescing the software results to produce a subset of the software results, generating a code search user interface comprising information indicative of the subset of software results, and causing presentation of the code search user interface and displaying the subset of software results.

Abstract: A chip for multi-die communications couplings using a single bridge die, includes: a plurality of dies each including one or more functional circuit blocks; and a first bridge die directly communicatively coupling two or more pairs of dies of the plurality of dies.

Abstract: Method and systems, performed by one or more processors, are disclosed. A method, performed by one or more processors, may comprise receiving a query for performing one or more computational operations on one or more multi-dimensional data sets representing multi-dimensional time series data collected in real-time from one or more sensors associated with one or more technical systems. The method may also comprise identifying the location of the one or more multi-dimensional time series data sets in one or more databases, retrieving the one or more multi-dimensional time series data sets from the identified one or more databases, and performing the one or more computational operations on the retrieved one or more multi-dimensional time series data sets. The method may also comprise generating output based on the result of the one or more computational operations indicative of one or more states of the one or more technical systems with respect to time.

Abstract: A content addressable memory (CAM) includes a first entry which includes one or more bits, a second entry which includes one or more bits, first comparison circuitry configured to compare each bit of a comparand to a corresponding bit of the one or more bits of the first entry and to provide a hit/miss indicator in response thereto, and second comparison circuitry configured to compare each bit of the one or more bits of the first entry to a corresponding bit of the one or more bits of the second entry and to provide a fault indicator in response thereto.

Abstract: A content addressable memory (CAM) includes a first entry which includes one or more bits, a second entry which includes one or more bits, first comparison circuitry configured to compare each bit of a comparand to a corresponding bit of the one or more bits of the first entry and to provide a hit/miss indicator in response thereto, and second comparison circuitry configured to compare each bit of the one or more bits of the first entry to a corresponding bit of the one or more bits of the second entry and to provide a fault indicator in response thereto.

Abstract: A system includes a plurality of sources to provide information access requests. An arbiter includes an assignment module to associate a first access request from the first source to one of the plurality of arbitration slots based upon assignment information at a storage location, and a dispatch module to determine one request of a plurality of requests received at the plurality of sources to be dispatched to a resource, memory controller by a dispatch module.

Abstract: A microprocessor architecture (310) has a plurality of functional units arranged in a parallel manner between one or more source buses (412 and/or 414) and one or more result buses (490). At least one of the functional units within the architecture is a content addressable memory (CAM) functional unit (430) which can be issued CPU instructions via a sequencer (480) much like any other functional unit. The operation of the CAM (430) may be pipelined in one or more stages so that the CAM's throughput may be increased to accommodate the higher clock rates that are likely used within the architecture (310). One embodiment involves pipelining the CAM operation in three stages (510, 520, and 530) in order to sequentially perform data input and precharge operations, followed by match operations, and followed Finally by priority encoding and data output.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying a monocrystalline substrate of a semiconductor structure by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. A semiconductor structure formed in accordance with this method includes a monocrystalline silicon substrate, a metal oxide semiconductor portion formed in the monocrystalline silicon substrate, and a compound semiconductor portion formed in the layer of monocrystalline compound semiconductor material.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

Abstract: Fault remediation functions are embodied in a semiconductor structure in which high quality epitaxial layers of monocrystalline materials are made to overlie monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Fault remediation is carried out in one instance by recognizing the presence of a fault and in another instance by providing fault correction.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart form a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

Abstract: A system employing synchronous clock signals utilizes the distribution of a fast clock signal along a forward path to clock generators for providing standard clock signals, and a recovery of such signal via a return path. The fast clock signal has a distinguishable portion, such as a periodic missing pulse or other anomaly, which is used to determine delay characteristics for the fast clock signal to the clock generators. A controllable delay corresponding to the forward path is adjusted, based on the determined delay characteristics, to synchronize delivery of the fast clock signal to the clock generators. Preferably, a significant portion of the clock generation and distribution system is formed on a semiconductor structure have a combination of compound semiconductor material and Group IV semiconductor material.

Abstract: An apparatus includes a memory system having multiple memory subsystems that are operable to concurrently service memory transactions. The memory system has an interface arrangement with an interconnection network that allows for independent access to each memory subsystem, and logic blocks that support the servicing and distribution or routing of memory transactions. Preferably, the apparatus is formed on a semiconductor structure having a combination of compound semiconductor material and Group IV semiconductor material.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. Mixed technology structures are provided in which a microprocessor is formed entirely in a monocrystalline compound semiconductor material layer overlying the silicon substrate.