Patents by Inventor Mihoko Tojo
Mihoko Tojo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9703695Abstract: A control device including a processor. The processor configured to allocate a data area of a memory device to a plurality of memory areas of data blocks of a first size; allocate identical data blocks of the first size to a plurality of the data areas of the memory device; manage management information indicating a data storing state of the plurality of memory areas of data blocks of the first size in each data area; determine, based on the management information regarding a plurality of data areas allocated with respect to a data block to be written, one data area from the plurality of data areas; and generate write data of a second size, which is different from the first size, including data of the data block to be written and write the write data in the one data area.Type: GrantFiled: February 3, 2014Date of Patent: July 11, 2017Assignee: FUJITSU LIMITEDInventors: Hidefumi Kobayashi, Yoshihito Konta, Atsushi Igashira, Koutarou Nimura, Marie Abe, Mihoko Tojo, Masatoshi Nakamura
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Patent number: 9529707Abstract: Write commands for a storage device specify write data with either a first data step size or a second data step size. In the former case, the storage device performs a read-modify-write (RMW) cycle which includes reading data with the second data step size. In the latter case, the storage device executes the command in a single write cycle. A command sorting unit sorts received commands into two groups, first commands and second commands, when storing them in a memory. First commands are write commands whose data boundaries do not match with the second data step size. Second commands include write commands whose data boundaries match with the second data step size. A command issuing unit converts first commands into a second command upon predetermined conditions. The command issuing unit issues the second commands to the storage device, in preference to the first commands.Type: GrantFiled: October 9, 2014Date of Patent: December 27, 2016Assignee: FUJITSU LIMITEDInventors: Masatoshi Nakamura, Koutarou Nimura, Marie Abe, Yoshihito Konta, Hidefumi Kobayashi, Mihoko Tojo, Yasuhiro Ogasawara, Shigeru Akiyama
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Patent number: 9195529Abstract: An information processing apparatus manages activation of a program by a task which is a unit of execution, and executes a task for each sequence in units of process block. The information processing apparatus has a nonvolatile memory which keeps an execution state management table. The execution state of the process block is stored in the execution state management table. The control unit performs a first activation procedure which initializes the execution state management table and, while updating the execution state in the execution state management table, executes the task. When activation by the first activation procedure has failed, the control unit performs activation by a second activation procedure and identifies a suspicious sequence. When activation by the second activation procedure has failed, the control unit performs activation by a third activation procedure and identifies a suspicious task.Type: GrantFiled: July 12, 2013Date of Patent: November 24, 2015Assignee: FUJITSU LIMITEDInventors: Yuusuke Oota, Hidefumi Kobayashi, Tatsuya Yanagisawa, Mihoko Tojo, Tsukasa Makino
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Publication number: 20150121021Abstract: Write commands for a storage device specify write data with either a first data step size or a second data step size. In the former case, the storage device performs a read-modify-write (RMW) cycle which includes reading data with the second data step size. In the latter case, the storage device executes the command in a single write cycle. A command sorting unit sorts received commands into two groups, first commands and second commands, when storing them in a memory. First commands are write commands whose data boundaries do not match with the second data step size. Second commands include write commands whose data boundaries match with the second data step size. A command issuing unit converts first commands into a second command upon predetermined conditions. The command issuing unit issues the second commands to the storage device, in preference to the first commands.Type: ApplicationFiled: October 9, 2014Publication date: April 30, 2015Inventors: Masatoshi Nakamura, Koutarou Nimura, Marie Abe, Yoshihito Konta, Hidefumi Kobayashi, Mihoko Tojo, Yasuhiro Ogasawara, Shigeru Akiyama
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Publication number: 20140289493Abstract: A control device including a processor. The processor configured to allocate a data area of a memory device to a plurality of memory areas of data blocks of a first size; allocate identical data blocks of the first size to a plurality of the data areas of the memory device; manage management information indicating a data storing state of the plurality of memory areas of data blocks of the first size in each data area; determine, based on the management information regarding a plurality of data areas allocated with respect to a data block to be written, one data area from the plurality of data areas; and generate write data of a second size, which is different from the first size, including data of the data block to be written and write the write data in the one data area.Type: ApplicationFiled: February 3, 2014Publication date: September 25, 2014Applicant: FUJITSU LIMITEDInventors: Hidefumi Kobayashi, Yoshihito Konta, Atsushi Igashira, Koutarou Nimura, Marie Abe, Mihoko Tojo, Masatoshi Nakamura
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Publication number: 20140059335Abstract: An information processing apparatus manages activation of a program by a task which is a unit of execution, and executes a task for each sequence in units of process block. The information processing apparatus has a nonvolatile memory which keeps an execution state management table. The execution state of the process block is stored in the execution state management table. The control unit performs a first activation procedure which initializes the execution state management table and, while updating the execution state in the execution state management table, executes the task. When activation by the first activation procedure has failed, the control unit performs activation by a second activation procedure and identifies a suspicious sequence. When activation by the second activation procedure has failed, the control unit performs activation by a third activation procedure and identifies a suspicious task.Type: ApplicationFiled: July 12, 2013Publication date: February 27, 2014Inventors: Yuusuke Oota, Hidefumi Kobayashi, TATSUYA YANAGISAWA, Mihoko Tojo, Tsukasa Makino
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Patent number: 8078908Abstract: An apparatus includes a cache memory for storing user data and control information of the apparatus, a nonvolatile memory and a processor for executing a process including when the power failure occurs, saving the user data and the control information stored in the cache memory into the nonvolatile memory, when the power failure recovers, restoring the data stored in the nonvolatile memory into the cache memory, and erasing the data stored in the nonvolatile memory after restoring the data into the cache memory and when another power failure occurs during erasing the data stored in the nonvolatile memory, erasing the control information stored in the nonvolatile memory if the control information is remained in the nonvolatile memory and saving, into the nonvolatile memory, the updated control information stored in the cache memory and the user data which has been erased from the nonvolatile memory.Type: GrantFiled: May 12, 2010Date of Patent: December 13, 2011Assignee: Fujitsu LimitedInventors: Mihoko Tojo, Hidefumi Kobayashi, Yusuke Oota, Satoshi Hayashi, Keiichi Umezawa
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Publication number: 20100299558Abstract: An apparatus includes a cache memory for storing user data and control information of the apparatus, a nonvolatile memory and a processor for executing a process including when the power failure occurs, saving the user data and the control information stored in the cache memory into the nonvolatile memory, when the power failure recovers, restoring the data stored in the nonvolatile memory into the cache memory, and erasing the data stored in the nonvolatile memory after restoring the data into the cache memory and when another power failure occurs during erasing the data stored in the nonvolatile memory, erasing the control information stored in the nonvolatile memory if the control information is remained in the nonvolatile memory and saving, into the nonvolatile memory, the updated control information stored in the cache memory and the user data which has been erased from the nonvolatile memory.Type: ApplicationFiled: May 12, 2010Publication date: November 25, 2010Applicant: FUJITSU LIMITEDInventors: Mihoko TOJO, Hidefumi Kobayashi, Yusuke Oota, Satoshi Hayashi, Keiichi Umezawa