Abstract: A digital signal processing system for executing instructions and processing data, including a program memory which stores the instructions and a first portion of the data, a data memory which stores a second portion of the data, and a program control unit connected to the program memory for receiving a sequence of the instructions and generating control signals for executing the instructions, wherein the program control unit is programmed to fetch at least one data value from the program memory in response to at least one of the instructions. Preferably, the system also includes a memory management unit connected to the program control unit and the data memory for generating address signals in response to at least one of the control signals for use in reading data values from the data memory.

Abstract: A circuit for performing either single precision or double precision arithmetic operations on data, a system including such a circuit, and a method implemented by the system. Preferably, the circuit is an arithmetic manipulation unit (AMU) which performs arithmetic operations on N-bit words in a single precision mode and on 2N-bit words in a double precision mode. The AMU concatenates two N-bit words in the double precision mode thus producing a 2N-bit operand, and performs a selected one of several arithmetic operations on the operand and a second 2N-bit operand. Preferably, the AMU performs a double precision operation in two cycles: a first cycle generating a first operand and loading the operand to an output register; and a second cycle in which a second operand is generated from a second pair of N-bit parts from the memory, the first operand is fed back from the output register, and an arithmetic operation is performed on the two operands.

Abstract: A digital signal processing system for executing instructions, including a program memory which stores the instructions and a program control unit for receiving and processing a sequence of the instructions to generate control signals for controlling operation of the system, and a loop circuit for use in such a program control unit. The loop circuit controls execution of a loop (preferably a nested loop) of a sequence of the instructions. Preferably, the loop circuit includes loop registers for storing loop start and end addresses and loop count values, and logic circuitry for implementing loops (including nested loops) in response to the addresses and count values in the loop registers. The loop circuit is initialized by loading appropriate addresses and values into the loop registers.

Abstract: An improved DSP has two internal data buses with two MAC units each receiving data from its respective data bus. A shifter is interposed between the multiply unit and the ALU and accumulate unit. The improved DSP also has a multiplexer interposed between one of the MAC units and the two data buses. The improved DSP is optimized to decode a received digital signal encoded in accordance with the Viterbi algorithm, wherein the DSP calculates a first pair of binary signals C.sub.2n and C.sub.2n+1 a Viterbi butterfly based upon a second pair of binary C.sub.n and C.sub.n+m/2, and a transitional signal a, in accordance with: C.sub.2n =minimum (C.sub.n +a, C.sub.n+m/2 -a); C.sub.2n+1 =minimum (C.sub.n -a, C.sub.n+m/2 +a).

Abstract: The multiply/divide circuit uses an exclusive OR function of an ALU in a DSP. The result of the exclusive OR function through accumulators and shift registers which recycle the shifted signals back to the ALU, can be made to perform the multiply or divide function. When used in a DSP for telecommunication purposes, the multiply/divide circuit can perform convolution encoding and cyclic redundancy check, among other functions, specifically for the telecommunication application.

Abstract: In a digital wireless communication system, a first unit transmits a digitally encoded signal to a second unit in a plurality of non-contiguous time slots. Within each time slot, the digitally encoded signal has a synchronization signal portion followed by a data signal portion. The second unit has an antenna to receive the synchronization signal portion of the digitally encoded signal. The second unit also has a clock to generate a clock signal at a first rate having a sampling phase. An analog to digital converter receives the clock signal and the synchronization signal and samples the synchronization signal at the first rate to generate a first plurality of symbols. An interpolator receives the first plurality of symbols and interpolates the first plurality of symbols to generate a second plurality of symbols at a second rate. The second rate is a multiple of the first rate.