Abstract: An interrupt management apparatus is provided for managing interrupt events generated by, for example, peripheral devices and computing modules. The interrupt management apparatus has an event decoder for receiving one or more interrupt signals from one or more interrupt sources and for decoding a received interrupt signal to produce control data relating to an interrupt event. The apparatus also has a sequence memory for storing one or more sequences, a sequence including one or more steps for handling one or more interrupt events, and one or more sequencers for interpreting one or more steps of a sequence stored in the sequence memory, the one or more sequencers being arranged to receive said control data from the event decoder. This enables the apparatus to manage said interrupt events without assistance from a central processing unit.

Abstract: A memory controller that allows shared access to a memory device via a plurality of write ports and read ports. A write port includes a data buffer that allows data to be written to a first number of its storage locations at a pre-determined time. A write arbiter is able to read data from a second number of storage locations of a data buffer of a write port at a pre-determined time and write the read data to a memory device. A read port is configured to respond to requests to read data and includes a data buffer. A read arbiter is able to read, at a pre-determined time, data from the memory device on behalf of one of the read ports, and to write the read data into a second number of storage locations of the data buffer of the read port on whose behalf the data was read.

Abstract: A memory controller that allows shared access to a memory device via a plurality of write ports and read ports. A write port includes a data buffer that allows data to be written to a first number of its storage locations at a pre-determined time. A write arbiter is able to read data from a second number of storage locations of a data buffer of a write port at a pre-determined time and write the read data to a memory device. A read port is configured to respond to requests to read data and includes a data buffer. A read arbiter is able to read, at a pre-determined time, data from the memory device on behalf of one of the read ports, and to write the read data into a second number of storage locations of the data buffer of the read port on whose behalf the data was read.

Abstract: An interrupt management apparatus is provided for managing interrupt events generated by, for example, peripheral devices and computing modules. The interrupt management apparatus has an event decoder for receiving one or more interrupt signals from one or more interrupt sources and for decoding a received interrupt signal to produce control data relating to an interrupt event. The apparatus also has a sequence memory for storing one or more sequences, a sequence including one or more steps for handling one or more interrupt events, and one or more sequencers for interpreting one or more steps of a sequence stored in the sequence memory, the one or more sequencers being arranged to receive said control data from the event decoder. This enables the apparatus to manage said interrupt events without assistance from a central processing unit.

Abstract: A memory controller that allows shared access to a memory device via a plurality of write ports and read ports. A write port includes a data buffer that allows data to be written to a first number of its storage locations at a pre-determined time. A write arbiter is able to read data from a second number of storage locations of a data buffer of a write port at a pre-determined time and write the read data to a memory device. A read port is configured to respond to requests to read data and includes a data buffer. A read arbiter is able to read, at a pre-determined time, data from the memory device on behalf of one of the read ports, and to write the read data into a second number of storage locations of the data buffer of the read port on whose behalf the data was read.