Abstract: A microphone circuit assembly for an external application processor, such as a programmable Digital Signal Processor, may include a microphone preamplifier and analog-to-digital converter to generate microphone signal samples at a first predetermined sample rate. A speech feature extractor is configured for receipt and processing of predetermined blocks of the microphone signal samples to extract speech feature vectors representing speech features of the microphone signal samples. The microphone circuit assembly may include a speech vocabulary comprising a target word or target phrase of human speech encoded as a set of target feature vectors and a decision circuit is configured to compare the speech feature vectors generated by the speech feature extractor with the target feature vectors to detect the target speech word or phrase.

Abstract: The present invention relates in one aspect to an audio amplification circuit comprising an input terminal for receipt of an input signal from a transducer. A signal processor is operatively coupled to the input terminal for receipt and processing of the input signal to generate a processed digital audio signal in accordance with a programmable configuration setting of the signal processor. A serial data transmission interface is configured for receipt of the processed digital audio signal and supply of a corresponding digital audio stream at an output terminal of the integrated audio amplification circuit. A serial data receipt interface is operatively coupled to an externally accessible configuration terminal of the integrated audio amplification circuit and a controller is configured to adjust one of the programmable configuration setting of the signal processor and a format of a digital audio stream in accordance with first configuration data received through the serial data receipt interface.

Abstract: Active Noise Cancellation (ANC) systems and methods that reduce latency to improve performance. In certain embodiments the systems sample a noise signal using a sample period to create a stream of digital signal data that is representative of the noise signal. A data transport layer carries the digital signal data to a signal processor. The transport layer temporally organizes the digital signal data to place the digital signal data within an initial phase of a sample period. The remaining phase of the sample period is set to a duration that allows the signal processor to process the digital signal data carried in the initial phase and to output the processed data during the same sample period. In this way, the processing of data occurs within one sample period and the latency is reduced and predictable.

Abstract: In at least one example embodiment, a microprocessor circuit is provided that includes a microprocessor core coupled to a data memory via a data memory bus comprising a predetermined integer number of data wires (J); the single-ported data memory configured for storage of vector input elements of an N element vector in a predetermined vector element order and storage of matrix input elements of an M×N matrix comprising M columns of matrix input elements and N rows of matrix input elements; a vector matrix product accelerator comprising a datapath configured for multiplying the N element vector and the matrix to compute an M element result vector, the vector matrix product accelerator comprising: an input/output port interfacing the data memory bus to the vector matrix product accelerator; a plurality of vector input registers for storage respective input vector elements received through the input/output port.

Abstract: An audio amplification circuit may include an input terminal for receipt of an input signal from a transducer. A signal processor may be coupled to the input terminal for receipt and processing of the input signal to generate a processed digital audio signal in accordance with a programmable configuration setting of the signal processor. A serial data transmission interface is configured for receipt of the processed digital audio signal and supply of a corresponding digital audio stream at an output terminal of the integrated audio amplification circuit. A serial data receipt interface may be coupled to an externally accessible configuration terminal of the integrated audio amplification circuit and a controller is configured to adjust one of the programmable configuration setting of the signal processor and a format of a digital audio stream in accordance with first configuration data received through the serial data receipt interface.

Abstract: A system for ultrasound beamforming is provided, including a sampled analog beamformer, an array of ultrasound transducers, and a high voltage amplifier coupled to the sampled analog beamformer and the array of ultrasound transducers. The sampled analog beamformer includes a sampled analog filter for filtering an incoming analog signal and adding a fractional delay, and transmitting a filtered analog ultrasound signal. The array of ultrasound transducers further transmits the filtered analog ultrasound signal. The high voltage amplifier drives transducers in the array of ultrasound transducers.

Abstract: A microprocessor circuit may include a software programmable microprocessor core and a data memory accessible via a data memory bus. The data memory may include sets of configuration data structured according to respective predetermined data structure specifications for configurable math hardware accelerators, and sets of input data for configurable math hardware accelerators, each configured to apply a predetermined signal processing function to the set of input data according to received configuration data. A configuration controller is coupled to the data memory via the data memory bus and to the configurable math hardware accelerators. The configuration controller may fetch the configuration data for each math hardware accelerator from the data memory and translate the configuration data.

Abstract: In at least one example embodiment, a microprocessor circuit is provided that includes a microprocessor core coupled to a data memory via a data memory bus comprising a predetermined integer number of data wires (J); the single-ported data memory configured for storage of vector input elements of an N element vector in a predetermined vector element order and storage of matrix input elements of an M×N matrix comprising M columns of matrix input elements and N rows of matrix input elements; a vector matrix product accelerator comprising a datapath configured for multiplying the N element vector and the matrix to compute an M element result vector, the vector matrix product accelerator comprising: an input/output port interfacing the data memory bus to the vector matrix product accelerator; a plurality of vector input registers for storage respective input vector elements received through the input/output port.

Abstract: An audio amplification circuit may include an input terminal for receipt of an input signal from a transducer. A signal processor may be coupled to the input terminal for receipt and processing of the input signal to generate a processed digital audio signal in accordance with a programmable configuration setting of the signal processor. A serial data transmission interface is configured for receipt of the processed digital audio signal and supply of a corresponding digital audio stream at an output terminal of the integrated audio amplification circuit. A serial data receipt interface may be coupled to an externally accessible configuration terminal of the integrated audio amplification circuit and a controller is configured to adjust one of the programmable configuration setting of the signal processor and a format of a digital audio stream in accordance with first configuration data received through the serial data receipt interface.

Abstract: A microphone circuit assembly for an external application processor, such as a programmable Digital Signal Processor, may include a microphone preamplifier and analog-to-digital converter to generate microphone signal samples at a first predetermined sample rate. A speech feature extractor is configured for receipt and processing of predetermined blocks of the microphone signal samples to extract speech feature vectors representing speech features of the microphone signal samples. The microphone circuit assembly may include a speech vocabulary comprising a target word or target phrase of human speech encoded as a set of target feature vectors and a decision circuit is configured to compare the speech feature vectors generated by the speech feature extractor with the target feature vectors to detect the target speech word or phrase.

Abstract: The present invention relates to power and hardware efficient digital multipliers configured to multiply an N-bit multiplicand with an M-bit multiplier. The digital multipliers comprise efficient partial product generation through sharing of at least one partial product result.