Patents by Inventor Mikal C. Hunsaker
Mikal C. Hunsaker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210389371Abstract: An apparatus comprises a first semiconductor chip comprising a first communication controller to receive first debug data from a second semiconductor chip; a memory to store the first debug data from the second semiconductor chip and second debug data of the first semiconductor chip; and a second communication controller to transmit the first debug data from the second semiconductor chip and the second debug data of the first semiconductor chip to an output port of the first semiconductor chip.Type: ApplicationFiled: August 30, 2021Publication date: December 16, 2021Applicant: Intel CorporationInventors: Vui Yong Liew, Zhenyu Zhu, Mikal C. Hunsaker, Wai Mun Ng
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Patent number: 11086812Abstract: An embedded controller is provided for a computer, including a processor, first one or more logic elements providing a serial peripheral interface (SPI) module to communicatively couple the embedded controller to an SPI bus as an SPI slave, and second one or more logic elements providing a platform environment control interface (PECI)-over-SPI engine, to build an SPI packet providing an encapsulated PECI command and send a notification to an SPI master that the packet is available.Type: GrantFiled: December 26, 2015Date of Patent: August 10, 2021Assignee: Intel CorporationInventors: Mikal C. Hunsaker, Shaun M. Conrad, Zhenyu Zhu, Navtej Singh
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Method, apparatus, and system for power management on a CPU die via clock request messaging protocol
Patent number: 11016549Abstract: Aspects of the embodiments are directed to systems, methods, and apparatuses for controlling power management states using a clock request message across a 3.3 volt GPIO pin. Systems can include a CPU root port to transmit to a platform controller hub (PCH) compliant with a PCIe protocol, a first clock request message, the first clock request message comprising a first bit set to assert a clock request transmit (CLKREQ TX assert) on a 3.3 volt general purpose input/output (GPIO) pin local to the PCH; detect that a connected device is entering into a power management state; and transmit, from the CPU root port, to the PCH, a second clock request message, the second clock request message comprising the first bit set to deassert the clock request transmit (CLKREQ TX deassert) and a second bit to assert a clock request protocol (CLKREQ#) on a 3.3 volt GPIO pin.Type: GrantFiled: January 12, 2018Date of Patent: May 25, 2021Assignee: Intel CorporationInventors: Poh Thiam Teoh, Mikal C. Hunsaker, Su Wei Lim, Gim Chong Lee, Hooi Kar Loo, Shashitheren Kerisnan, Siang Lin Tan, Ming Chew Lee, Ngeok Kuan Wai, Li Len Lim -
Patent number: 10719469Abstract: A method implemented by a system on a chip (SOC) system executing an enhance serial peripheral interconnect (eSPI) master. The method to receive an alert from an eSPI slave, send a get out of band message to the eSPI slave, and receive an out of band message from the eSPI slave including a connection or disconnection command. The method enabling the SOC to include an embedded multiplexor for managing the role of a universal serial bus (USB) Type-C connector.Type: GrantFiled: February 28, 2017Date of Patent: July 21, 2020Assignee: INTEL CORPORATIONInventors: Zhenyu Zhu, Mikal C Hunsaker, Christopher J. Lake, Kie Woon Lim
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Patent number: 10229080Abstract: In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.Type: GrantFiled: July 17, 2015Date of Patent: March 12, 2019Assignee: Intel CorporationInventors: Ting Lok Song, Su Wei Lim, Mikal C. Hunsaker, Hooi Kar Loo
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METHOD, APPARATUS, AND SYSTEM FOR POWER MANAGEMENT ON A CPU DIE VIA CLOCK REQUEST MESSAGING PROTOCOL
Publication number: 20190041936Abstract: Aspects of the embodiments are directed to systems, methods, and apparatuses for controlling power management states using a clock request message across a 3.3 volt GPIO pin. Systems can include a CPU root port to transmit to a platform controller hub (PCH) compliant with a PCIe protocol, a first clock request message, the first clock request message comprising a first bit set to assert a clock request transmit (CLKREQ TX assert) on a 3.3 volt general purpose input/output (GPIO) pin local to the PCH; detect that a connected device is entering into a power management state; and transmit, from the CPU root port, to the PCH, a second clock request message, the second clock request message comprising the first bit set to deassert the clock request transmit (CLKREQ TX deassert) and a second bit to assert a clock request protocol (CLKREQ#) on a 3.3 volt GPIO pin.Type: ApplicationFiled: January 12, 2018Publication date: February 7, 2019Inventors: Poh Thiam Teoh, Mikal C. Hunsaker, Su Wei Lim, Gim Chong Lee, Hooi Kar Loo, Shashitheren Kerisnan, Siang Lin Tan, Ming Chew Lee, Ngeok Kuan Wai, Li Len Lim -
Patent number: 10185385Abstract: A method and apparatus to reduce the idle link power in a platform. In one embodiment of the invention, the host and its coupled endpoint(s) in the platform each has a low power idle link state that allows disabling of the high speed link circuitry in both the host and its coupled endpoint(s). This allows the platform to reduce its idle power as both the host and its coupled endpoint(s) are able to turn off their high speed link circuitry in one embodiment of the invention.Type: GrantFiled: June 13, 2016Date of Patent: January 22, 2019Assignee: Intel CorporationInventors: Paul S. Diefenbaugh, Robert E. Gough, Yuval Bachrach, Mikal C. Hunsaker, Rafi Ben-Tal, Ilan Pardo, Gideon Prat, David J. Harriman
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Patent number: 10164880Abstract: In one embodiment, the present invention is directed to method for receiving a packet in a first agent, where the packet includes a first packet header with an expanded header indicator. Based on this indicator, the agent can determine if the packet includes one or more additional packet headers. If so, the agent can next determining if it supports information in the additional packet header based on a header identifier of the additional header. Other embodiments are described and claimed.Type: GrantFiled: November 14, 2014Date of Patent: December 25, 2018Assignee: Intel CorporationInventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Rohit R. Verma, Robert P. Adler
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Patent number: 10157160Abstract: In one embodiment, a method includes: receiving, via a sideband interface of a multi-root agent associated with a first root space and a second root space, a reset prepare signal to inform the multi-root agent that the first root space is to be reset; sending, via the sideband interface, an acknowledgement signal to acknowledge the reset prepare signal; receiving one or more transactions for the first root space from a fabric coupled to the multi-root agent; and terminating the one or more transactions responsive to the reset prepare signal, where the first root space is in a reset state when the one or more transactions are received. Other embodiments are described and claimed.Type: GrantFiled: September 25, 2015Date of Patent: December 18, 2018Assignee: Intel CorporationInventors: Michael T. Klinglesmith, Mikal C. Hunsaker, William Knolla, Hartej Singh
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Patent number: 10146715Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.Type: GrantFiled: January 24, 2017Date of Patent: December 4, 2018Assignee: Intel CorporationInventors: Mikal C. Hunsaker, Su Wei Lim, Ricardo E. James
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Publication number: 20180246830Abstract: A method implemented by a system on a chip (SOC) system executing an enhance serial peripheral interconnect (eSPI) master. The method to receive an alert from an eSPI slave, send a get out of band message to the eSPI slave, and receive an out of band message from the eSPI slave including a connection or disconnection command. The method enabling the SOC to include an embedded multiplexor for managing the role of a universal serial bus (USB) Type-C connector.Type: ApplicationFiled: February 28, 2017Publication date: August 30, 2018Inventors: Zhenyu ZHU, Mikal C HUNSAKER, Christopher J. LAKE, Kie Woon LIM
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Patent number: 9921987Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.Type: GrantFiled: July 25, 2016Date of Patent: March 20, 2018Assignee: Intel CorporationInventors: Mikal C. Hunsaker, Su Wei Lim, Ricardo E. James
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Patent number: 9910814Abstract: Techniques and mechanisms for exchanging single-ended communications with a protocol stack of an integrated circuit package. In an embodiment, an integrated circuit (IC) chip includes a protocol stack comprising a transaction layer which performs operations compatible with a Peripheral Component Interconnect Express™ (PCIe™) specification. Transaction layer packets, exchanged between the transaction layer and a link layer of the protocol stack, are compatible with a PCIe™ format. In another embodiment, a physical layer of the protocol stack is to couple the IC chip to another IC chip for an exchange of the transaction layer packets via single-ended communications. A packaged device includes both of the IC chips.Type: GrantFiled: March 13, 2015Date of Patent: March 6, 2018Assignee: INTEL CORPORATIONInventors: Bryan L. Spry, Su Wei Lim, Mikal C. Hunsaker, Rohit R. Verma, Lily P. Looi, Ronald W. Swartz, Michael W. Leddige, Vui Yong Liew
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Patent number: 9753875Abstract: In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.Type: GrantFiled: January 20, 2016Date of Patent: September 5, 2017Assignee: Intel CorporationInventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Mohan K. Nair, Joseph Murray, Rohit R. Verma, Gary J. Lavelle, Robert P. Adler
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Publication number: 20170185559Abstract: An embedded controller is provided for a computer, including a processor, first one or more logic elements providing a serial peripheral interface (SPI) module to communicatively couple the embedded controller to an SPI bus as an SPI slave, and second one or more logic elements providing a platform environment control interface (PECI)-over-SPI engine, to build an SPI packet providing an encapsulated PECI command and send a notification to an SPI master that the packet is available.Type: ApplicationFiled: December 26, 2015Publication date: June 29, 2017Inventors: Mikal C. Hunsaker, Shaun M. Conrad, Zhenyu Zhu, Navtej Singh
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Patent number: 9658978Abstract: In one embodiment, a system-on-chip (SoC) can be configured to receive a request from a master agent in a fabric coupled to the master agent, send a show command grant to the master agent responsive to selection of the request by the fabric, receive a command portion of a transaction corresponding to the request in the fabric and determine a target agent to receive the transaction based on the command portion, and thereafter send a transaction grant to the master agent for the transaction. Other embodiments are described and claimed.Type: GrantFiled: March 13, 2014Date of Patent: May 23, 2017Assignee: Intel CorporationInventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Eran Tamari, Joseph Murray, Robert P. Adler
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Publication number: 20170132171Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.Type: ApplicationFiled: January 24, 2017Publication date: May 11, 2017Applicant: Intel CorporationInventors: Mikal C. Hunsaker, Su Wei Lim, Ricardo E. James
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Publication number: 20170123475Abstract: A method and apparatus to reduce the idle link power in a platform. In one embodiment of the invention, the host and its coupled endpoint(s) in the platform each has a low power idle link state that allows disabling of the high speed link circuitry in both the host and its coupled endpoint(s). This allows the platform to reduce its idle power as both the host and its coupled endpoint(s) are able to turn off their high speed link circuitry in one embodiment of the invention.Type: ApplicationFiled: June 13, 2016Publication date: May 4, 2017Inventors: Paul S. Diefenbaugh, Robert E. Gough, Yuval Bachrach, Mikal C. Hunsaker, Rafi Ben-Tal, Ilan Pardo, Gideon Prat, David J. Harriman
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Patent number: 9619416Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.Type: GrantFiled: March 25, 2015Date of Patent: April 11, 2017Assignee: Intel CorporationInventors: Mikal C. Hunsaker, Su Wei Lim, Ricardo E. James
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Patent number: 9588922Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.Type: GrantFiled: March 25, 2015Date of Patent: March 7, 2017Assignee: Intel CorporationInventors: Mikal C. Hunsaker, Su Wei Lim, Ricardo E. James