Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

Abstract: In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.

Abstract: In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.

Abstract: Systems and methods may provide for securely transferring data from a flash component. In one example, the method may include receiving a download request from an embedded controller chip, obtaining information from the flash component in response to the download request, and transferring the information to the embedded controller chip.

Abstract: In some embodiments, an electronic system includes a processor, a memory in communication with the processor, a bus in communication with the processor, an Express Card controller coupled to the bus, the Express Card controller providing an interface to an external device, a USB3 controller coupled to the bus and in communication with the Express Card controller, and a PCIE controller coupled to the bus and in communication with the Express Card controller. The Express Card controller may be configured to determine whether the external device is a USB3 device or a PCIE device and to switch between the USB3 controller and the PCIE controller based on the state of a USB3 select pin strap. Other embodiments are disclosed and claimed.

Abstract: A power reduction proposal for a receiver circuit that adheres to a plurality of defined states and masking logic to mask the output of the squelch receiver. Furthermore, the proposal utilizes and counters to count the various timeout conditions. Consequently, the squelch receiver consumes less power and can be either powered down or periodically enabled to allow for polling.

Abstract: An embodiment of the present invention is an efficient interconnecting bus. A first clock source generates a first clock signal at a first frequency on a link bus line synchronized with first data to be transmitted to a device. The device has a second clock source to generate a second clock signal at a second frequency synchronized with second data when the device transmits the second data. The first and second data each forms a packet being one of a posted, completion, and non-posted packets. The first and second frequencies are independent of each other and bounded within first and second frequency ranges, respectively. A queue structure stores packets used in a credit-based flow control policy.

Abstract: An apparatus, method, and system are disclosed. In one embodiment, the apparatus includes a clock source unit that generates a clock signal, multiple clock trunk lines that supply the clock signal to multiple devices, and a clock control unit that instructs the clock source unit that can gate or supply the clock signal on the clock trunk lines.

Abstract: A power reduction proposal for a receiver circuit that adheres to a plurality of defined states and masking logic to mask the output of the squelch receiver. Furthermore, the proposal utilizes and counters to count the various timeout conditions. Consequently, the squelch receiver consumes less power and can be either powered down or periodically enabled to allow for polling.

Abstract: Embodiments of token hold off techniques for a token based communication interconnect are presented herein.

Abstract: An embodiment of the present invention is an efficient interconnecting bus. A first clock source generates a first clock signal at a first frequency on a link bus line synchronized with first data to be transmitted to a device. The device has a second clock source to generate a second clock signal at a second frequency synchronized with second data when the device transmits the second data. The first and second data each forms a packet being one of a posted, completion, and non-posted packets. The first and second frequencies are independent of each other and bounded within first and second frequency ranges, respectively. A queue structure stores packets used in a credit-based flow control policy.

Abstract: A management controller configured to generate and transmit transport layer packets to send management messages to a plurality of recipients managed by the management controller, co-disposed on the same computing platform, is disclosed and described herein. The managed recipients may be coupled to the management controller via buses of different bus types. The management controller is configured to logically address the managed recipients, to automatically split a management message over multiple packets when constrained by data bandwidth of a bus of a particular bus type, or to appropriately format the transport layer packets for the different buses of different bus types.

Abstract: Various embodiments adjust the rate at which periodic flow control updates are transmitted when in a lower power or power saving state. One embodiment transmits flow control updates across a bus based upon a first rate in response to a normal power mode and transmits second flow control updates across the bus based upon a second rate in response to a power saving mode.

Abstract: A computer system that detects for a PCI Express compliant endpoint device is described. Specifically, the computer system clocks transmit and receive circuits at a first frequency and initiates a training sequence. If the endpoint device successfully trains at the first frequency, the endpoint device is PCI Express compliant. Otherwise, the computer system initiates another training sequence at a second frequency.

Abstract: Apparatus and method are disclosed that control the issuance of posted and non-posted requests. Some embodiments maintain a specified period between successive non-posted requests on a bus. The specific period may be based upon an expected time for a non-posted request to complete on the bus and the configuration of the link.

Abstract: Method and apparatus for arbitrating prioritized cycle streams in a manner that prevents starvation. High priority and low priority arbitration pools are employed for arbitrating multiple input cycle streams. Each cycle stream contains a stream of requests of a given type and associated priority. Under normal circumstances in which resource buffer availability for a destination device is not an issue, higher priority streams are provided grants over lower priority streams, with all streams receiving grants. However, when a resource buffer is not available for a lower priority stream, arbitration of high priority streams with available buffer resources are redirected to the low priority arbitration pool, resulting in generation of grant counts for both the higher and lower priority streams.

Abstract: Transaction layer link down handling for Peripheral Component Interconnect (PCI) Express. A link between an input/output (I/O) controller port of an I/O controller and a device port of a device is initialized, wherein the link includes a physical layer, a data link layer, and a transaction layer. The transaction layer is restored after a data link down condition without software intervention.

Abstract: Queue resource sharing for an input/output controller. A shared resource queue is associated with a plurality of ports. The shared resource queue includes a plurality of sections allocated for use by at least one of the plurality of ports based at least in part on a port bandwidth configuration of the plurality of ports.

Abstract: Method and apparatus for programmable completion tracking logic to support multiple virtual channels. In one embodiment, the apparatus includes a controller having the programmable completion tracking logic for supporting multiple virtual channels. In one embodiment, a completion tracking queue is programmable to provide a predetermined number of entries to store upstream non-posted (NP) read request information corresponding to a virtual channel from a plurality of virtual channels supported by the controller. In one embodiment, the predetermined number of entries are shared among the plurality of virtual channels according to a minimum entry value and a maximum entry value defined for each respective virtual channel. Other embodiments are described and claimed.