Patents by Inventor Mike Bertone
Mike Bertone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10782896Abstract: A method for managing an observed order of instructions in a computing system includes utilizing an overloaded memory barrier instruction to specify whether a global ordering constraint or a local ordering constraint is enforced.Type: GrantFiled: January 4, 2019Date of Patent: September 22, 2020Assignee: Marvell Asia Pte, Ltd.Inventors: Shubhendu Sekhar Mukherjee, Richard Eugene Kessler, Mike Bertone, Chris Comis, Bryan Chin
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Patent number: 10339054Abstract: Execution of the memory instructions is managed using memory management circuitry including a first cache that stores a plurality of the mappings in the page table, and a second cache that stores entries based on virtual addresses. The memory management circuitry executes operations from the one or more modules, including, in response to a first operation that invalidates at least a first virtual address, selectively ordering each of a plurality of in progress operations that were in progress when the first operation was received by the memory management circuitry, wherein a position in the ordering of a particular in progress operation depends on either or both of: (1) which of one or more modules initiated the particular in progress operation, or (2) whether or not the particular in progress operation provides results to the first cache or second cache.Type: GrantFiled: February 7, 2018Date of Patent: July 2, 2019Assignee: Cavium, LLCInventors: Shubhendu Sekhar Mukherjee, Albert Ma, Mike Bertone
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Publication number: 20190138232Abstract: A method for managing an observed order of instructions in a computing system includes utilizing an overloaded memory barrier instruction to specify whether a global ordering constraint or a local ordering constraint is enforced.Type: ApplicationFiled: January 4, 2019Publication date: May 9, 2019Inventors: Shubhendu Sekhar Mukherjee, Richard Eugene Kessler, Mike Bertone, Chris Comis, Bryan Chin
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Patent number: 10216430Abstract: A method for managing an observed order of instructions in a computing system includes utilizing an overloaded memory barrier instruction to specify whether a global ordering constraint or a local ordering constraint is enforced.Type: GrantFiled: August 31, 2015Date of Patent: February 26, 2019Assignee: Cavium, LLCInventors: Shubhendu Sekhar Mukherjee, Richard Eugene Kessler, Mike Bertone, Chris Comis, Bryan Chin
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Publication number: 20180165197Abstract: Execution of the memory instructions is managed using memory management circuitry including a first cache that stores a plurality of the mappings in the page table, and a second cache that stores entries based on virtual addresses. The memory management circuitry executes operations from the one or more modules, including, in response to a first operation that invalidates at least a first virtual address, selectively ordering each of a plurality of in progress operations that were in progress when the first operation was received by the memory management circuitry, wherein a position in the ordering of a particular in progress operation depends on either or both of: (1) which of one or more modules initiated the particular in progress operation, or (2) whether or not the particular in progress operation provides results to the first cache or second cache.Type: ApplicationFiled: February 7, 2018Publication date: June 14, 2018Inventors: Shubhendu Sekhar Mukherjee, Albert Ma, Mike Bertone
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Patent number: 9910776Abstract: Execution of the memory instructions is managed using memory management circuitry including a first cache that stores a plurality of the mappings in the page table, and a second cache that stores entries based on virtual addresses. The memory management circuitry executes operations from the one or more modules, including, in response to a first operation that invalidates at least a first virtual address, selectively ordering each of a plurality of in progress operations that were in progress when the first operation was received by the memory management circuitry, wherein a position in the ordering of a particular in progress operation depends on either or both of: (1) which of one or more modules initiated the particular in progress operation, or (2) whether or not the particular in progress operation provides results to the first cache or second cache.Type: GrantFiled: November 14, 2014Date of Patent: March 6, 2018Assignee: Cavium, Inc.Inventors: Shubhendu Sekhar Mukherjee, Albert Ma, Mike Bertone
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Publication number: 20170286315Abstract: Managing translation invalidation includes: in response to determining that a first invalidation message (IM) applies to a subset of virtual addresses (VAs) consisting of fewer than all VAs associated with a first set of translation context (TC) values, searching VA-indexed structure(s) to find and invalidate any entries that correspond to a VA in the subset; in response to determining that a second IM applies to all VAs associated with a second set of TC values and that no entry exists in invalidation-tracking structure(s) corresponding to the second set, bypassing searching any VA-indexed structure(s); and in response to determining that a third IM applies to all VAs associated with a third set of TC values and that at least one entry exists in the invalidation-tracking structure(s) corresponding to the third set, storing invalidation information in the invalidation-tracking structure(s) to invalidate the third set and delaying searching any VA-indexed structure(s).Type: ApplicationFiled: April 1, 2016Publication date: October 5, 2017Inventors: Shubhendu Sekhar Mukherjee, Mike Bertone
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Patent number: 9779028Abstract: Managing translation invalidation includes: in response to determining that a first invalidation message (IM) applies to a subset of virtual addresses (VAs) consisting of fewer than all VAs associated with a first set of translation context (TC) values, searching VA-indexed structure(s) to find and invalidate any entries that correspond to a VA in the subset; in response to determining that a second IM applies to all VAs associated with a second set of TC values and that no entry exists in invalidation-tracking structure(s) corresponding to the second set, bypassing searching any VA-indexed structure(s); and in response to determining that a third IM applies to all VAs associated with a third set of TC values and that at least one entry exists in the invalidation-tracking structure(s) corresponding to the third set, storing invalidation information in the invalidation-tracking structure(s) to invalidate the third set and delaying searching any VA-indexed structure(s).Type: GrantFiled: April 1, 2016Date of Patent: October 3, 2017Assignee: CAVIUM, INC.Inventors: Shubhendu Sekhar Mukherjee, Mike Bertone
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Patent number: 9684606Abstract: Managing a plurality of translation lookaside buffers (TLBs) includes: issuing, at a first processing element, a first instruction for invalidating one or more TLB entries associated with a first context in a first TLB associated with the first processing element. The issuing includes: determining whether or not a state of an indicator indicates that all TLB entries associated with the first context in a second TLB associated with a second processing element are invalidated; if not: sending a corresponding instruction to the second processing element, causing invalidation of all TLB entries associated with the first context in the second TLB, and changing a state of the indicator; and if so: suppressing sending of any corresponding instructions for causing invalidation of any TLB entries associated with the first context in the second TLB to the second processing element.Type: GrantFiled: November 14, 2014Date of Patent: June 20, 2017Assignee: CAVIUM, INC.Inventors: Richard Eugene Kessler, Shubhendu Sekhar Mukherjee, Mike Bertone
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Publication number: 20170003905Abstract: A method for managing an observed order of instructions in a computing system includes utilizing an overloaded memory barrier instruction to specify whether a global ordering constraint or a local ordering constraint is enforced.Type: ApplicationFiled: August 31, 2015Publication date: January 5, 2017Inventors: Shubhendu Sekhar Mukherjee, Richard Eugene Kessler, Mike Bertone, Chris Comis, Bryan Chin
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Patent number: 9501425Abstract: Each of multiple translation lookaside buffers (TLBs) is associated with a corresponding processing element. A first TLB invalidation (TLBI) instruction is issued at a first processing element, and sent to a second processing element. An element-specific synchronization instruction is issued at the first processing element. A synchronization command is broadcast, and received at the second processing element. The element-specific synchronization instruction prevents issuance of additional TLBI instructions at the first processing element until an acknowledgement in response to the synchronization command is received at the first processing element.Type: GrantFiled: November 14, 2014Date of Patent: November 22, 2016Assignee: Cavium, Inc.Inventors: Shubhendu S. Mukherjee, David Asher, Mike Bertone, Bradley Dobbie, Thomas Hummel
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Patent number: 9405702Abstract: A core executes memory instructions. A memory management unit (MMU) coupled to the core includes a first cache that stores a plurality of final mappings of a hierarchical page table, a page table walker that traverses levels of the page table to provide intermediate results associated with respective levels for determining the final mappings, and a second cache that stores a limited number of intermediate results provided by the page table walker. The MMU compares a portion of the first virtual address to portions of entries in the second cache, in response to a request from the core to invalidate a first virtual address, based on a match criterion that depends on the level associated with each intermediate result stored in an entry in the second cache, and removes any entries in the second cache that satisfy the match criterion.Type: GrantFiled: November 14, 2014Date of Patent: August 2, 2016Assignee: Cavium, Inc.Inventors: Shubhendu Sekhar Mukherjee, Mike Bertone, Albert Ma
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Publication number: 20160140048Abstract: A core executes memory instructions. A memory management unit (MMU) coupled to the core includes a first cache that stores a plurality of final mappings of a hierarchical page table, a page table walker that traverses levels of the page table to provide intermediate results associated with respective levels for determining the final mappings, and a second cache that stores a limited number of intermediate results provided by the page table walker. The MMU compares a portion of the first virtual address to portions of entries in the second cache, in response to a request from the core to invalidate a first virtual address, based on a match criterion that depends on the level associated with each intermediate result stored in an entry in the second cache, and removes any entries in the second cache that satisfy the match criterion.Type: ApplicationFiled: November 14, 2014Publication date: May 19, 2016Inventors: Shubhendu Sekhar Mukherjee, Mike Bertone, Albert Ma
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Publication number: 20160140051Abstract: Managing a plurality of translation lookaside buffers (TLBs) includes: issuing, at a first processing element, a first instruction for invalidating one or more TLB entries associated with a first context in a first TLB associated with the first processing element. The issuing includes: determining whether or not a state of an indicator indicates that all TLB entries associated with the first context in a second TLB associated with a second processing element are invalidated; if not: sending a corresponding instruction to the second processing element, causing invalidation of all TLB entries associated with the first context in the second TLB, and changing a state of the indicator; and if so: suppressing sending of any corresponding instructions for causing invalidation of any TLB entries associated with the first context in the second TLB to the second processing element.Type: ApplicationFiled: November 14, 2014Publication date: May 19, 2016Inventors: Richard Eugene Kessler, Shubhendu Sekhar Mukherjee, Mike Bertone
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Publication number: 20160140047Abstract: Each of multiple translation lookaside buffers (TLBs) is associated with a corresponding processing element. A first TLB invalidation (TLBI) instruction is issued at a first processing element, and sent to a second processing element. An element-specific synchronization instruction is issued at the first processing element. A synchronization command is broadcast, and received at the second processing element. The element-specific synchronization instruction prevents issuance of additional TLBI instructions at the first processing element until an acknowledgement in response to the synchronization command is received at the first processing element.Type: ApplicationFiled: November 14, 2014Publication date: May 19, 2016Inventors: Shubhendu Sekhar Mukherjee, David Asher, Mike Bertone, Brad Dobbie, Tom Hummel
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Publication number: 20160140043Abstract: Execution of the memory instructions is managed using memory management circuitry including a first cache that stores a plurality of the mappings in the page table, and a second cache that stores entries based on virtual addresses. The memory management circuitry executes operations from the one or more modules, including, in response to a first operation that invalidates at least a first virtual address, selectively ordering each of a plurality of in progress operations that were in progress when the first operation was received by the memory management circuitry, wherein a position in the ordering of a particular in progress operation depends on either or both of: (1) which of one or more modules initiated the particular in progress operation, or (2) whether or not the particular in progress operation provides results to the first cache or second cache.Type: ApplicationFiled: November 14, 2014Publication date: May 19, 2016Inventors: Shubhendu Sekhar Mukherjee, Albert Ma, Mike Bertone