Patents by Inventor Mike Jadon
Mike Jadon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11003586Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.Type: GrantFiled: February 5, 2020Date of Patent: May 11, 2021Assignee: Radian Memory Systems, Inc.Inventors: Robert Lercari, Alan Chen, Mike Jadon, Craig Robertson, Andrey V. Kuzmin
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Patent number: 10983907Abstract: This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage.Type: GrantFiled: March 28, 2020Date of Patent: April 20, 2021Assignee: Radian Memory Systems, Inc.Inventors: Andrey V. Kuzmin, Mike Jadon, Richard M. Mathews
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Patent number: 10977188Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.Type: GrantFiled: February 3, 2020Date of Patent: April 13, 2021Assignee: Radian Memory Systems, Inc.Inventors: Robert Lercari, Alan Chen, Mike Jadon, Craig Robertson, Andrey V. Kuzmin
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Patent number: 10915458Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.Type: GrantFiled: February 3, 2020Date of Patent: February 9, 2021Assignee: Radian Memory Systems, Inc.Inventors: Robert Lercari, Alan Chen, Mike Jadon, Craig Robertson, Andrey V. Kuzmin
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Patent number: 10884915Abstract: This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage.Type: GrantFiled: June 16, 2017Date of Patent: January 5, 2021Assignee: Radian Memory Systems, Inc.Inventors: Andrey V. Kuzmin, Mike Jadon, Richard M. Mathews
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Patent number: 10838853Abstract: This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage.Type: GrantFiled: June 16, 2017Date of Patent: November 17, 2020Assignee: Radian Memory Systems, Inc.Inventors: Andrey V. Kuzmin, Mike Jadon, Richard M. Mathews
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Patent number: 10642748Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.Type: GrantFiled: August 29, 2017Date of Patent: May 5, 2020Assignee: Radian Memory Systems, Inc.Inventors: Robert Lercari, Alan Chen, Mike Jadon, Craig Robertson, Andrey V. Kuzmin
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Patent number: 10552058Abstract: Processing functions are offloaded to a memory controller for nonvolatile memory by a host in connection with write data. The nonvolatile memory executes these functions, producing processed data that must be written into memory; for example, the offloaded functions can include erasure coding, with the nonvolatile memory controller generating redundancy information that must be written into memory. The memory controller holds this information in internal RAM and then later writes this information into nonvolatile memory according to dynamically determined write time and/or destinations selected by the host, so as to not collide with host data access requests. In one embodiment, the memory is NAND flash memory and the memory controller is a cooperative memory controller that permits the host to schedule concurrent operations in respective, configurable virtual block devices which have been configured by the host out of a pool of structural flash memory structures managed by the memory controller.Type: GrantFiled: July 15, 2016Date of Patent: February 4, 2020Assignee: Radian Memory Systems, Inc.Inventors: Mike Jadon, Craig Robertson, Robert Lercari
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Patent number: 9785572Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.Type: GrantFiled: March 18, 2016Date of Patent: October 10, 2017Assignee: Radian Memory Systems, Inc.Inventors: Robert Lercari, Alan Chen, Mike Jadon, Craig Robertson, Andrey V. Kuzmin
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Patent number: 9727454Abstract: This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage.Type: GrantFiled: August 22, 2014Date of Patent: August 8, 2017Assignee: Radian Memory Sytems, Inc.Inventors: Andrey V. Kuzmin, Mike Jadon, Richard M. Mathews
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Patent number: 9652376Abstract: This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage.Type: GrantFiled: February 14, 2013Date of Patent: May 16, 2017Assignee: Radian Memory Systems, Inc.Inventors: Andrey V. Kuzmin, Mike Jadon, Richard M. Mathews
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Patent number: 9588904Abstract: Hierarchical address virtualization within a memory controller and configurable block device allocation are disclosed. Respective virtual block devices (VBDs) are defined in flash memory managed by a common memory controller, with data access managed using address virtualization techniques. The common memory controller then tracks the need for maintenance operations independently for each VBD. Information may be received from the common memory controller regarding the need for maintenance operations in respective virtual block devices (VBDs), and commands are then selectively issued to the common memory controller in a manner so as to independently schedule these operations for the respective VBDs; performance of maintenance operations by the memory controller in a first VBD is unconstrained by performance characteristics associated with a second VBD.Type: GrantFiled: February 25, 2016Date of Patent: March 7, 2017Assignee: Radian Memory Systems, Inc.Inventors: Robert Lercari, Alan Chen, Mike Jadon, Craig Robertson, Andrey V. Kuzmin
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Patent number: 9542118Abstract: This disclosure provides techniques of hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.Type: GrantFiled: October 12, 2015Date of Patent: January 10, 2017Assignee: Radian Memory Systems, Inc.Inventors: Robert Lercari, Alan Chen, Mike Jadon, Craig Robertson, Andrey V. Kuzmin
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Patent number: 9400749Abstract: This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage.Type: GrantFiled: January 28, 2016Date of Patent: July 26, 2016Assignee: Radian Memory Systems, LLCInventors: Andrey V. Kuzmin, Mike Jadon, Richard M. Mathews
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Publication number: 20140365719Abstract: This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage.Type: ApplicationFiled: August 22, 2014Publication date: December 11, 2014Inventors: Andrey V. Kuzmin, Mike Jadon, Richard M. Mathews
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Publication number: 20140215129Abstract: This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage.Type: ApplicationFiled: February 14, 2013Publication date: July 31, 2014Applicant: Radian Memory Systems, LLCInventors: Andrey V. Kuzmin, Mike Jadon, Richard M. Mathews
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Patent number: 7293197Abstract: An NVRAM fail-over controller including a NVRAM device connected to a host computer, the host computer having the ability to directly control the NVRAM device. The NVRAM fail-over controller includes an embedded processor that is powered by back-up power. The NVRAM fail-over controller includes a network interface that is powered by back-up power.Type: GrantFiled: April 14, 2004Date of Patent: November 6, 2007Assignee: Micro Memory LLCInventors: Mike Jadon, Robert Lercari, Richard M. Mathews, William R. Peebles, Phap Nguyen, Mark Kampe
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Publication number: 20050039090Abstract: An NVRAM fail-over controller including a NVRAM device connected to a host computer, the host computer having the ability to directly control the NVRAM device. The NVRAM fail-over controller includes an embedded processor that is powered by back-up power. The NVRAM fail-over controller includes a network interface that is powered by back-up power.Type: ApplicationFiled: April 14, 2004Publication date: February 17, 2005Inventors: Mike Jadon, Robert Lercari, Richard Mathews, William Peebles, Phap Nguyen, Mark Kampe
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Publication number: 20050038958Abstract: A host-NVRAM disk-array controller that can be connected to a host computer. The controller including an NVRAM, a plurality of disk array controllers, and a plurality of busses. The NVRAM is connected to a memory controller (together called the NVRAM device). The host computer has the ability to directly control the NVRAM device. The plurality of busses connect the NVRAM device and the disk array controllers.Type: ApplicationFiled: April 14, 2004Publication date: February 17, 2005Inventors: Mike Jadon, Robert Lercari, Richard Mathews, William Peebles, Phap Nguyen