Patents by Inventor Mike Van Buskirk

Mike Van Buskirk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6266275
    Abstract: A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: July 24, 2001
    Assignees: Advanced Micro Devices, Inc., Fujitsu Limited
    Inventors: Paul-Ling Chen, Mike Van Buskirk, Shane Charles Hollmer, Binh Quang Le, Shoichi Kawamura, Chung-You Hu, Yu Sun, Sameer Haddad, Chi Chang
  • Patent number: 5999452
    Abstract: A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground.
    Type: Grant
    Filed: April 21, 1998
    Date of Patent: December 7, 1999
    Assignees: Advanced Micro Devices, Inc., Fujitsu Limited
    Inventors: Pau-Ling Chen, Mike Van Buskirk, Shane Charles Hollmer, Binh Quang Le, Shoichi Kawamura, Chung-You Hu, Yu Sun, Sameer Haddad, Chi Chang
  • Patent number: 5912489
    Abstract: A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: June 15, 1999
    Assignees: Advanced Micro Devices, Inc., Fujitsu Limited
    Inventors: Pau-Ling Chen, Mike Van Buskirk, Shane Charles Hollmer, Binh Quang Le, Shoichi Kawamura, Chung-You Hu, Yu Sun, Sameer Haddad, Chi Chang