Abstract: An electronic device includes routing logic operatively coupled to a communication port that is externally accessible so that there is no need to disassemble the electronic device to gain access. The port may be a USB (universal serial bus) port and provides access to an internal bus. The routing logic is also operatively coupled to a memory subsystem such that it may route data from an external device, connected at the port, to the memory subsystem to modify or replace a boot code, including a BIOS code. A memory interface device includes an interface module, a memory interface module for communicating with a memory subsystem including a boot PROM (programmable read only memory), and a routing logic coupled to the interface module and the memory interface module. The routing logic routes data from the external device to the boot PROM, so that a boot code, including a BIOS (basic input/output system), may be modified or replaced.

Abstract: An apparatus, method, and system are provided as a solution for computer operation. An embodiment of the apparatus includes a device that interconnects the core of the computer through the memory interface. The apparatus provides a communication path from the computer core to the world wide network. Computing communication and storage functions of the conventional computer are incorporated in the apparatus. The purpose of the apparatus is to enable the computer data and program to flow into and out of the computer core without being stored on a peripheral device such a disk or other media.

Abstract: An apparatus, method, and system are provided for optimizing computer operation. An embodiment of the apparatus includes a device that interconnects the core of the computer through the memory interface. The apparatus provides a communication path from the computer core to the world wide network. Computing communication and storage functions of the conventional computer are incorporated in the apparatus. Thus this improved computer architecture can operate with superior performance without disk and without operating system. This novel architecture permits to application software designers to develop software applications targeting this novel computer architecture rather than various the operating systems.

Abstract: An apparatus, method, and system are provided for optimizing computer performance while a first processor is in a sleep mode of operation. For example, an embodiment of the apparatus includes a first processor, a second processor (also referred to herein as a “sleep” processor), and one or more peripheral devices. When the first processor is in a sleep mode of operation, the sleep processor is configured to control one or more functions of the computer system incorporating the first processor and the sleep processor. These functions can include applications that may not otherwise be executed while the first processor is in sleep mode such as, for example, functions of the one or more peripheral devices. As a result, power management of the computer system is improved since the first processor remains in sleep mode for a longer period of time.

Abstract: A memory device includes memory sleep logic operative to detect a repetitive pattern within at least one memory block, and place the memory block into a sleep mode in response to detecting the repetitive pattern. The memory device memory sleep logic may also provide a response to read commands to the memory block while it is in sleep mode, where the response is a constant output for any address location of the memory block. The memory device memory sleep logic may include pattern detection logic, associated with each memory block, to detect the repetitive pattern; and data port logic, coupled to the pattern detection logic, operative to receive an activation command from the pattern detection logic, and operative to return a constant output pattern in response to any read command to read data from the memory block.

Abstract: An electronic device includes routing logic operatively coupled to a communication port that is externally accessible so that there is no need to disassemble the electronic device to gain access. The port may be a USB port and provides access to an internal bus. The routing logic is also operatively coupled to a memory subsystem such that it may route data from an external device, connected at the port, to the memory subsystem to modify or replace a boot code, including a BIOS code. A memory interface device includes an interface module, a memory interface module for communicating with a memory subsystem including a boot PROM, and a routing logic coupled to the interface module and the memory interface module. The routing logic routes data from the external device to the boot PROM, so that a boot code, including a BIOS, may be modified or replaced.

Abstract: A memory device includes memory sleep logic operative to detect a repetitive pattern within at least one memory block, and place the memory block into a sleep mode in response to detecting the repetitive pattern. The memory device memory sleep logic may also provide a response to read commands to the memory block while it is in sleep mode, where the response is a constant output for any address location of the memory block. The memory device memory sleep logic may include pattern detection logic, associated with each memory block, to detect the repetitive pattern; and data port logic, coupled to the pattern detection logic, operative to receive an activation command from the pattern detection logic, and operative to return a constant output pattern in response to any read command to read data from the memory block.