Abstract: An apparatus, method, and system are provided for optimizing computer performance while a first processor is in a sleep mode of operation. For example, an embodiment of the apparatus includes a first processor, a second processor (also referred herein as a “sleep” processor), and one or more peripheral devices. The peripheral devices are coupled to the first processor and the sleep processor through a computer bus architecture. During an active mode of operation, the first processor interacts with and controls the functions of the peripheral devices. In an embodiment, the sleep processor also interacts with and controls the functions of the peripheral devices during the active mode of operation. However, when the first processor is in a sleep mode of operation, the sleep processor is configured to control one or more functions of the computer system incorporating the first processor and the sleep processor.