Patents by Inventor Mikhail Chetin

Mikhail Chetin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230331257
    Abstract: Disclosed are systems and methods for responding to unsupported or degraded conditions for autonomous vehicles (AVs). In some aspects, a method includes aggregating one or more trigger events generated across a software stack of an autonomous vehicle (AV) as aggregated trigger events, the one or more trigger events indicating at least one of unsupported or degraded conditions that bring the AV outside of allowable driving conditions of the AV, ranking the aggregated trigger events in accordance with priority levels corresponding to the aggregated trigger events, determining an AV maneuver to respond to a selected trigger event, wherein the selected trigger event is a highest ranked trigger event of the aggregated trigger events, causing the AV maneuver to be performed by the AV, and determining whether to at least one of fail the AV or recover the AV to a normal driving state in response to the selected trigger event.
    Type: Application
    Filed: April 19, 2022
    Publication date: October 19, 2023
    Applicant: GM CRUISE HOLDINGS LLC
    Inventors: Tucker Allen Paxton, Lucio Otavio Marchioro Rech, Yang Tian, Mikhail Chetin
  • Patent number: 10430536
    Abstract: An approach is described for yield calculation using statistical timing data that accounts for path and stage delay correlation. Embodiments of the present invention provide an improved approach for yield calculation using statistical timing data that accounts for path and stage delay correlation. According to some embodiments, the approach includes receiving statistical timing analysis data, identifying paths for performing timing analysis, performing timing analysis where common segments of different paths are analyzed using shared data and where subsequent stages are transformed to provide an expected correlation between stages, and generating yield probability results based on at least the results of calculating timing analysis.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 1, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Igor Keller, Praveen Ghanta, Mikhail Chetin
  • Patent number: 10275554
    Abstract: A method as provided includes retrieving a correlation value from a correlation table and a coskewness value from a coskewness table. The correlation value includes a correlation between a delay distribution and a slew rate distribution, and is associated with both: an input slew rate and an output load, in a logic stage in an integrated circuit design, and the coskewness value is a coskewness between the delay distribution and the slew rate distribution. The method includes determining a partial derivative of a delay function relative to the input slew rate, determining a delay distribution for a signal through a plurality of logic stages using the correlation value, the coskewness value, and the partial derivative of the delay function relative to the input slew rate. The method also includes verifying that a statistical value of the delay distribution satisfies a desired performance value for an integrated circuit.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: April 30, 2019
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Mikhail Chetin, Igor Keller, Praveen Ghanta
  • Patent number: 9710593
    Abstract: Disclosed are techniques for enhancing timing analyses with reduced timing libraries for electronic designs. These techniques determine dominance relations for multiple timing models for timing analyses and generate a dominance adjacency data structure based at least in part upon the dominance relations. The dominance adjacency data structure may be stored at a first location of a non-transitory computer accessible storage medium. The plurality of timing models may be reduced into a reduced set of timing models at least by providing the dominance adjacency data structure as an input to a transformation and further by transforming the dominance adjacency data structure with the transformation into the reduced set of timing models that are used in timing analyses for an electronic design or a portion thereof.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: July 18, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Igor Keller, Mikhail Chetin, Xiaojun Sun