Patents by Inventor Mikhail Shirokov
Mikhail Shirokov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10855383Abstract: A system and a method for calibrating an antenna using trim bits and non-volatile memory is disclosed. In one aspect, an apparatus includes a power amplifier configured to at least amplify the output signal of the first antenna. The power amplifier includes multiple stages. The apparatus further includes a trim control circuit configured to adjust a bias of one of the stages of the power amplifier, using trim bits from non-volatile memory. The trim control circuit is further configured to scale the bias of one of the plurality of stages of the power amplifier by an integer between 0 and 2n?1 corresponding to a binary number formed by the first plurality of trim bits, wherein n corresponds to the number of trim bits.Type: GrantFiled: March 14, 2019Date of Patent: December 1, 2020Assignee: ANOKIWAVE, INC.Inventors: Robert McMorrow, Vipul Jain, Mikhail Shirokov, Kevin B. Greene, Susanne A. Paul, Shamsun Nahar
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Publication number: 20200295853Abstract: A system and a method for calibrating an antenna using trim bits and non-volatile memory is disclosed. In one aspect, an apparatus includes a power amplifier configured to at least amplify the output signal of the first antenna. The power amplifier includes multiple stages. The apparatus further includes a trim control circuit configured to adjust a bias of one of the stages of the power amplifier, using trim bits from non-volatile memory. The trim control circuit is further configured to scale the bias of one of the plurality of stages of the power amplifier by an integer between 0 and 2n-1 corresponding to a binary number formed by the first plurality of trim bits, wherein n corresponds to the number of trim bits.Type: ApplicationFiled: March 14, 2019Publication date: September 17, 2020Applicant: ANOKIWAVE, INC.Inventors: Robert McMorrow, Vipul Jain, Mikhail Shirokov, Kevin B. Greene, Susanne A. Paul, Shamsun Nahar
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Patent number: 8509682Abstract: A switch element includes a switch device having a drain, a source and a plurality of gates, and at least one additional interconnect located between the plurality of gates, the additional interconnect operative to establish a constant potential between the at least two gates.Type: GrantFiled: April 2, 2012Date of Patent: August 13, 2013Assignee: Skyworks Solutions, Inc.Inventors: Dima Prikhodko, Jerod F. Mason, Steven P. Matte, John Pessia, Jason Chiesa, Sergey Nabokin, Gene A. Tkachenko, Richard A. Carter, Steven C. Sprinkle, Mikhail Shirokov
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Publication number: 20120190313Abstract: A switch element includes a switch device having a drain, a source and a plurality of gates, and at least one additional interconnect located between the plurality of gates, the additional interconnect operative to establish a constant potential between the at least two gates.Type: ApplicationFiled: April 2, 2012Publication date: July 26, 2012Applicant: Skyworks Solutions, Inc.Inventors: Dima Prikhodko, Jerod F. Mason, Steven P. Matte, John Pessia, Jason Chiesa, Sergey Nabokin, Gene A. Tkachenko, Richard A. Carter, Steven C. Sprinkle, Mikhail Shirokov
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Patent number: 8175523Abstract: A switch element includes a switch device having a drain, a source and a plurality of gates, and at least one additional interconnect located between the plurality of gates, the additional interconnect operative to establish a constant potential between the at least two gates.Type: GrantFiled: December 29, 2010Date of Patent: May 8, 2012Assignee: Skyworks Solutions, Inc.Inventors: Dima Prikhodko, Jerod F. Mason, Steven P. Matte, John Pessia, Jason Chiesa, Sergey Nabokin, Gene A. Tkachenko, Richard A. Carter, Steven C. Sprinkle, Mikhail Shirokov
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Publication number: 20110151776Abstract: A switch element includes a switch device having a drain, a source and a plurality of gates, and at least one additional interconnect located between the plurality of gates, the additional interconnect operative to establish a constant potential between the at least two gates.Type: ApplicationFiled: December 29, 2010Publication date: June 23, 2011Applicant: SKYWORKS SOLUTIONS, INC.Inventors: Dima Prikhodko, Jerod F. Mason, Steven P. Matte, John Pessia, Jason Chiesa, Sergey Nabokin, Gene A. Tkachenko, Richard A. Carter, Steven C. Sprinkle, Mikhail Shirokov
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Patent number: 7877058Abstract: A switch element includes a switch device having a drain, a source and a plurality of gates, and at least one additional interconnect located between the plurality of gates, the additional interconnect operative to establish a constant potential between the at least two gates.Type: GrantFiled: November 6, 2007Date of Patent: January 25, 2011Assignee: Skyworks Solutions, Inc.Inventors: Dima Prikhodko, Jerod F. Mason, Steven P. Matte, John Pessia, Jason Chiesa, Sergey Nabokin, Gene A. Tkachenko, Richard A. Carter, Steven C. Sprinkle, Mikhail Shirokov
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Patent number: 7492209Abstract: According to one exemplary embodiment, a low harmonic switching device includes a first switching block including a first multi-gate FET, where the first switching block is coupled to a first input and a shared output of the low harmonic switching device. A first capacitor is coupled between a first gate and a source of the first multi-gate FET and a second capacitor is coupled between a second gate and a drain of the first multi-gate FET so as to cause a reduction in a harmonic amplitude in the shared output. A resistor can couple the source to the drain of the first multi-gate FET. The first switching block can further include a second multi-gate FET, where a source of the second multi-gate FET is coupled to the drain of the first multi-gate FET and a drain of the second multi-gate FET is coupled to the shared output.Type: GrantFiled: July 24, 2006Date of Patent: February 17, 2009Assignee: Skyworks Solutions, Inc.Inventors: Dima Prikhodko, Sergey Nabokin, Steven C. Sprinkle, Mikhail Shirokov, Gene A. Tkachenko, Jason Chiesa
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Publication number: 20080166981Abstract: A switch element includes a switch device having a drain, a source and a plurality of gates, and at least one additional interconnect located between the plurality of gates, the additional interconnect operative to establish a constant potential between the at least two gates.Type: ApplicationFiled: November 6, 2007Publication date: July 10, 2008Inventors: Dima Prikhodko, Jerod F. Mason, Steven P. Matte, John Pessia, Jason Chiesa, Sergey Nabokin, Gene A. Tkachenko, Richard A. Carter, Steven C. Sprinkle, Mikhail Shirokov
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Patent number: 7304541Abstract: A voltage regulator integrated with a monolithic microwave integrated circuit (MMIC) power amplifier that supplies a regulated bias current to the MMIC power amplifier that is compensated for temperature and voltage supply variations. The regulator circuit includes HBT transistors for current mirrors and a voltage regulator where a base-emitter voltage drop compensates for a similar base emitter drop in the current mirrors. The regulator circuit is designed to maintain constant the bias voltage and mirror currents with changes in Vcc and temperature. The compensated constant bias current to the MMIC power amplifier maintains uniform operating parameters for the power amplifier.Type: GrantFiled: August 3, 2005Date of Patent: December 4, 2007Assignee: Fairchild Semiconductor CorporationInventors: Atiqul Baree, Mikhail Shirokov
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Publication number: 20070243849Abstract: According to one exemplary embodiment, a low harmonic switching device includes a first switching block including a first multi-gate FET, where the first switching block is coupled to a first input and a shared output of the low harmonic switching device. A first capacitor is coupled between a first gate and a source of the first multi-gate FET and a second capacitor is coupled between a second gate and a drain of the first multi-gate FET so as to cause a reduction in a harmonic amplitude in the shared output. A resistor can couple the source to the drain of the first multi-gate FET. The first switching block can further include a second multi-gate FET, where a source of the second multi-gate FET is coupled to the drain of the first multi-gate FET and a drain of the second multi-gate FET is coupled to the shared output.Type: ApplicationFiled: July 24, 2006Publication date: October 18, 2007Inventors: Dima Prikhodko, Sergey Nabokin, Steven C. Sprinkle, Mikhail Shirokov, Gene A. Tkachenko, Jason Chiesa
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Patent number: 7157966Abstract: A power amplifier includes an input network, output stages, coupled in parallel and configured to output power optimally in corresponding power-ranges, the output stages coupled to the input network, an output impedance matching network, coupled to the output stages and not containing a switching element, and a bias-control network, coupled between the output impedance matching network, the input network, and the output stages. In some amplifiers the output impedance matching network does not contain a switching element corresponding to the output stage configured to output power in the highest range. In other amplifiers the bias-control network is configured to isolate output stages by providing a hard shut-off to transistors of the isolated output stages.Type: GrantFiled: December 17, 2004Date of Patent: January 2, 2007Assignee: Fairchild Semiconductor CorporationInventors: Atiqul Baree, Gary Hau, Mikhail Shirokov, James A. Roche, Jr.
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Publication number: 20060284684Abstract: A voltage regulator integrated with a monolithic microwave integrated circuit (MMIC) power amplifier that supplies a regulated bias current to the MMIC power amplifier that is compensated for temperature and voltage supply variations. The regulator circuit includes HBT transistors for current mirrors and a voltage regulator where a base-emitter voltage drop compensates for a similar base emitter drop in the current mirrors. The regulator circuit is designed to maintain constant the bias voltage and mirror currents with changes in Vcc and temperature. The compensated constant bias current to the MMIC power amplifier maintains uniform operating parameters for the power amplifier.Type: ApplicationFiled: August 3, 2005Publication date: December 21, 2006Inventors: Atiqul Baree, Mikhail Shirokov
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Publication number: 20060132232Abstract: A power amplifier includes an input network, output stages, coupled in parallel and configured to output power optimally in corresponding power-ranges, the output stages coupled to the input network, an output impedance matching network, coupled to the output stages and not containing a switching element, and a bias-control network, coupled between the output impedance matching network, the input network, and the output stages. In some amplifiers the output impedance matching network does not contain a switching element corresponding to the output stage configured to output power in the highest range. In other amplifiers the bias-control network is configured to isolate output stages by providing a hard shut-off to transistors of the isolated output stages.Type: ApplicationFiled: December 17, 2004Publication date: June 22, 2006Inventors: Atiqul Baree, Gary Hau, Mikhail Shirokov, James Roche