Abstract: Each of processing nodes and switching apparatuses constituting a parallel processor system is provided with data transmitting/receiving apparatuses 100 and 200. The data transmitting/receiving apparatus 100, in response to an instruction from a processor P within its own node, transmits data stored in a transfer data buffer 110 to the data transmitting/receiving apparatus 200 of a switching apparatus connected thereto. The data transmitting/receiving apparatus 200 receives data that are transferred, and stores them into a transfer data buffer 210. If any error in receive data is detected by an error detector 214 of the data transmitting/receiving apparatus 200, a retransmission request signal 10 is issued from a retransmission control circuit 215 to the retransmission control circuit 114 of the transmitting apparatus 100. The retransmission control circuit 114, upon receiving the retransmission request signal 10, instructs a data transmission control signal 112 to execute retransmission.

Abstract: Each of processors in a multiprocessor system has a circuit for sending a synchronizing signal to a storage controller (SC) connected thereto when executing a synchronization instruction such as a start, end or barrier synchronization instruction. Each of the SCs has a circuit for notifying the corresponding processor of establishment of a synchronization upon detection of completion of a check to be made by an address management table FAA and of the issuing of necessary cache cancel requests corresponding to a store instruction issued before the synchronization instruction and upon recognition of the fact that all the processors have sent their synchronizing signals and that the issuing of all the cache cancel requests have been complete.