Abstract: According to an embodiment, a computer program product includes a computer-readable medium including program, when executed by a computer, to have a plurality of modules run by the computer. The computer includes a memory having a shared area, which is an area accessible to only those modules which run cooperatively and storing therein execution module identifiers. Each of the modules includes a first operation configured to store, just prior to a switchover of operations to an other module that runs cooperatively, an identifier of the other module as the execution module identifier in the shared area; and a second operation configured to execute, when the execution module identifier stored in the shared area matches with an identifier of own module immediately after a switchover of operations from the other module, a function inside the own module.

Abstract: A microprocessor executes programs in a pipeline architecture that includes a task register management unit that switches a value of a task register to second register information that is used when a second task is executed after the execution of a first task is completed, if a switch instruction to the second task is issued when a plurality of units executes the first task, and a task manager that switches a value of a task identification information register to a second task identifier after the value is switched to the second register information, and grants each of the plurality of units permission to execute the second task.

Abstract: A control device includes: a random number generating unit that generates a random number; a first setting unit that sets the random number in a first storage; a message creating unit that encrypts the random number using a public key of the administrative server and to create a request message to be transmitted to the administrative server; a timer starting unit that starts a timer; an activation unit that activates the system software; a timer canceling unit that accepts an interruption from the system software and cancels the timer; a message verifying unit that verifies the notification message from the administrative server using the public key and the random number; and a restart unit that restarts the system software while limiting the functions, in the case where the timer expires time or the verification fails.

Abstract: The debugging unit writes a public key of the key issuing server and an initializing program given from outside, to the storage unit. The instruction executing unit reads and executes the initializing program stored in the storage unit. The debug disabling unit disables the debugging unit. The public-key encrypting unit encrypts the random number by the public key in the storage unit, the random number generated by the random number generating unit after the debugging unit is disabled. The transmitting unit transmits the encrypted random number to the key issuing server. The receiving unit receives an individual key encrypted by the random number from the key issuing server. The individual-key writing unit decrypts the encrypted individual key by the random number to obtain the individual key and write the individual key to the storage unit.

Abstract: A microprocessor having a processor core includes an information acquisition unit that acquires information encrypted to be used by the processor core, from outside; a decryption unit that decrypts the information with a symmetric key to obtain plain text; and a controller that controls processing on the information acquired by the information acquisition unit based on the symmetric key.

Abstract: According to an embodiment, a memory management device increments a lower value of a first counter, updates the counter by incrementing an upper value and resetting the lower value when the lower value overflows, increments to update the lower counter value when the upper value is incremented as a result of writing a second data piece having the upper value in common to a memory, recalculates a first secret value calculated using the first counter values and a root secret value in response to the first counter update, writes a first data piece and the first secret value to the memory, and at reading of the first data piece and the first secret value, calculates a second secret value using the updated first counter values and the root secret value, and compares the first secret value with the second secret value to verify the first data piece.

Abstract: According to one embodiment, there is provided a an information processing apparatus, including: a program acceptance portion; a program storage portion; a first function type storage portion; a function type extraction portion; a second function type storage portion; a first alternate function type storage portion; an alternate function type extraction portion; a second alternate function type storage portion; a selection portion; a judging portion; an updating portion; and a protection attribute determination portion.

Abstract: According to one embodiment, an information processing device stores a program list and plural types of security functions each defining therein protection attributes for respective arguments related to input and output of data to be protected, and stores function argument protection attributes and dependency relations each of which is defined by a determinant set and a dependent attribute that satisfy a predetermined condition.

Abstract: A microprocessor executes programs in a pipeline architecture that includes a task register management unit that switches a value of a task register to second register information that is used when a second task is executed after the execution of a first task is completed, if a switch instruction to the second task is issued when a plurality of units executes the first task, and a task manager that switches a value of a task identification information register to a second task identifier after the value is switched to the second register information, and grants each of the plurality of units permission to execute the second task.

Abstract: A pressure sensor module of the invention includes a pressure sensor and a laminar substrate. Electrodes are arranged in the vicinity of a diaphragm portion of the pressure sensor. In the laminar substrate, a plurality of substrates are laminated, and the laminar substrate incorporates the pressure sensor. One face of the diaphragm portion is exposed by a space portion. According to the invention, it is possible to provide a pressure sensor module which facilitates smaller and thinner sizes, and which enables high-density packaging.

Abstract: A microprocessor executes programs in a pipeline architecture including a task register management unit that, if a switch instruction to a second task is issued when a plurality of units executes a first task, switches a value of a task register to second register information that is used when the second task is executed after the execution of the first task is completed and a task manager that switches a value of a task identification information register to a second task identifier after the value is switched to the second register information, and grants each of the plurality of units permission to execute the second task.

Abstract: A computer readable storage medium encoded with computer instructions for causing a tamper resistant microprocessor which has a function for decrypting and executing encrypted codes and a table formed by a plurality of regions for storing a plurality of encryption keys corresponding to at least one program and at least one shared library to be called up by the at least one program, to use a shared library called up from a calling source program, the instructions including the steps of causing the tamper resistant microprocessor to create a task for the shared library, causing the tamper resistant microprocessor to allocate a task identifier to the task, causing the tamper resistant microprocessor to acquire an instruction key from a header of the shared library, causing the tamper resistant microprocessor to store the instruction key into a region of the table corresponding to the task identifier allocated to the task for the shared library in the microprocessor, causing the tamper resistant microprocessor to

Abstract: A microprocessor includes a decryption unit that decrypts information to be utilized by a processor core to obtain plaintext information when the acquired information is encrypted; and a plaintext information storing unit that stores the plaintext information. The microprocessor also includes a protected attribute adding unit that adds a protected attribute indicating one of protection and non-protection to the plaintext information based on whether the decryption has been performed; an access request acquiring unit that acquires an access request to the plaintext information; a request type identifying unit that identifies a type of request of the access request; and an access controlling unit that controls an access to the plaintext information based on the type of request and the protected attribute.

Abstract: In a microprocessor, a program key for decrypting a program and a data key for encrypting/decrypting data processed by the program are handled as cryptographically inseparable pair inside the microprocessor, so that it becomes possible for the microprocessor to protect processes that actually execute the program, without an intervention of the operating system, and it becomes possible to conceal secret information of the program not only from the other user program but also from the operating system.

Abstract: A tamper resistant microprocessor has a task state table for assigning a task identifier to a task that can take a plurality of states, and storing a state of the task in correspondence to the task identifier; a task register for storing the task identifier of a currently executed task; an interface for reading a program stored in a form encrypted by using a program key at an external memory, in units of cache lines, when a request for the task is made; an encryption processing unit for generating decryption keys that are different for different cache lines, according to the program key, and decrypt a content read by the interface; a cache memory formed by a plurality of cache lines each having a tag, for storing the task identifier corresponding to a decryption key used in decrypting each cache line in the tag of each cache line; and an access check unit for comparing the task identifier stored in the tag of each cache line with a value of the task register, and discarding a content of each cache line when t

Abstract: In the method for sharing encrypted data region among two or more processes on a tamper resistant processor, one process creates the encrypted data region to be shared according to the common key generated as a result of the safe key exchange, and the other process maps that region to its own address space or process space. The address information of the shared encrypted data region and the common key of each process are set in relation in the encrypted attribute register inside the tamper resistant processor, so that it is possible to share the encrypted data region safely.

Abstract: A scheme for realizing a contents protection procedure between devices that are not connected to the same network, in a system where the IEEE 1394 buses are connected together through a 1394 bridge or a system where the IEEE 1394 buses are connected together through another radio network, is disclosed. A network connection device notifies information regarding a transmission node on the first IEEE 1394 bus to a reception node on the second IEEE 1394 bus, so that the reception node can carry out the authentication and key exchange procedure directly with the transmission node on a different network.

Abstract: An automobile part comprising a polypropylene resin composition, the polypropylene resin composition comprising a propylene homopolymer (A1), an elastomer (B) and an inorganic filler (C) in specified proportions. The polypropylene homopolymer (A1) exhibits an MFR (230° C.) of 20 to 300 g/10 min, a ratio of position irregular units derived from 2,1-insertion or 1,3-insertion of propylene monomer relative to all propylene structural units, determined from a 13C-NMR spectrum, each of 0.05% or less, and an Mw/Mn, determined by GPC, of 1 to 3.

Abstract: A microprocessor includes a first information holding unit, a second information holding unit, and a switching authorization unit. The first information holding unit holds process identification information and authentication information which are associated with each other. The second information holding unit denies access from outside, and holds entry information of a process and the authentication information which are associated with each other. The switching authorization unit allows switching process when the authentication information held in the first information holding unit with the authentication information held in the second information holding unit match.

Abstract: A pressure sensor module of the invention includes a pressure sensor and a laminar substrate. Electrodes are arranged in the vicinity of a diaphragm portion of the pressure sensor. In the laminar substrate, a plurality of substrates are laminated, and the laminar substrate incorporates the pressure sensor. One face of the diaphragm portion is exposed by a space portion. According to the invention, it is possible to provide a pressure sensor module which facilitates smaller and thinner sizes, and which enables high-density packaging.