Abstract: To enhance a drain current voltage characteristics of a compound semiconductor field effect transistor, an n-GaAs substrate is used. After forming an n.sup.- -GaAs layer and an i-AlGaAs layer successively on the substrate, an n-type transistor is formed on these layers. Subsequently, on the rear side of the n-GaAs substrate, an ohmic electrode is formed, to connect with a drain electrode on a surface side. In the structure, when a drain current is increased, at a drain side electron also flows toward the substrate, so that the current concentration on a drain region is relaxed. Thereby, the drain current voltage characteristics can be improved.

Abstract: A semiconductor device includes a bias circuit for applying a bias to a transistor in which the semiconductor comprises a two-terminal element, connected between an external power source and at least an input of the transistor, having a first conductive contact layer connected to the input of the transistor, a second conductive contact layer connected to the external power source, and a semiconductor layer having a semi-insulation intervened between the first and second conductive contact layers, thereby reducing the thermal runaway caused by temperature rise.

Abstract: On a semi-insulative GaAs substrate, a n-type GaAs layer, an undoped InGaAs layer, a n.sup.+ -type GaAs layer are grown in order and a SiO.sub.2 layer is deposited thereon. Subsequently, a photoresist layer having an opening at a gate region is formed. With taking the photoresist layer as a mask, side etching is performed for the SiO.sub.2 layer up to the width corresponding to a recess width. With taking SiO.sub.2 layer as a mask, wet etching is performed for n.sup.+ -type GaAs layer. The wet etching is further extended to the intermediate depth position of the undoped InGaAs layer. By lift off method employing the photoresist layer, a gate electrode is formed on the center of the bottom of the recess. A source electrode and a drain electrode are also formed. Thus, since the corner portions of the recess is formed of a material (InGaAs) difficult to cause dislocation, the compound semiconductor field effect transistor can prevent degradation of characteristics in high temperature burn-in test.

Abstract: A FET has comb-shaped electrode assemblies for source, drain and gate of the FET. Each of the source and drain electrode assemblies has a plurality of electrodes contacting the active region of the FET and formed as a first layer metal laminate, and a bus bar connecting the electrodes together to a corresponding pad and formed as a second layer metal laminate. The gate electrode layer has a plurality of gate electrodes contacting the active layer in Schottky contact, a gate bus bar connecting the gate electrodes together, a gate pad connected to the gate bus bar. The gate bus bar is formed as a first layer metal laminate intersecting the stem portion of the comb-shaped source bus bar. The two-layer metal structure of the FET reduces the number of photolithographic steps and thereby fabrication costs of the FET.