Abstract: A semiconductor device capable of efficiently increasing a capacity of a mounted storage element while achieving space saving, and an electronic apparatus including this semiconductor device are provided. The semiconductor device includes a storage element including a filament that has a first conductive layer, a second conductive layer, and an insulation layer. The first conductive layer and the second conductive layer are stacked with at least the insulation layer interposed between the first conductive layer and the second conductive layer. The filament obtains at least three identifiable resistance states by changing a combination of a state of the first conductive layer, a state of the second conductive layer, and a state of the insulation layer. The semiconductor device further includes a writing unit that produces the at least three identifiable resistance states by applying a blow current to the storage element.

Abstract: [Object] To provide a novel examination method for a cancer treatment effect, screening method for a peptide for a cancer vaccine, and peptide and composition for inducing an immune response against cancer. [Solving Means] Provided are an examination method for a cancer treatment effect and a screening method for a peptide for a cancer vaccine each including detecting an antibody against a cancer/testis antigen or an anti-p53 antibody in a sample. It is suitable that an anti-XAGE1 antibody (IgG and/or IgA) be detected, or an anti-NY-ESO-1 antibody (IgG) be detected. Also provided are a novel peptide and novel composition for inducing immune responses against cancer.

Abstract: A memory cell array of the present disclosure includes a plurality of memory cells 11 arranged in a first direction and a second direction different from the first direction. Each of the memory cells 11 includes a resistance-variable nonvolatile memory element and a selection transistor TR electrically connected to the nonvolatile memory element. The selection transistor TR is formed in an active region 80 provided in a semiconductor layer 60. At least a part of the active region 80 is in contact with an element isolation region 81 provided in the semiconductor layer 60. A surface of the element isolation region 81 is located at a position lower than a surface of the active region 80.

Abstract: Provided is a semiconductor device having a structure suitable for higher integration. The semiconductor device includes a transistor that includes a gate section, a first diffusion layer, and a second diffusion layer. The semiconductor device further includes a first electrically-conductive section a second electrically-conductive section that is electrically insulated from the first electrically-conductive section, a first storage element that is located between the first diffusion layer and the first electrically-conductive section and is electrically coupled to each of the first diffusion layer and the first electrically-conductive section, and a second storage element that is located between the second diffusion layer and the second electrically-conductive section and is electrically coupled to each of the second diffusion layer and the second electrically-conductive section.

Abstract: A nonvolatile memory cell includes a resistance-change nonvolatile memory element 50 and a selection transistor TR. One end of the nonvolatile memory element 50 is connected to one source/drain region 15A of the selection transistor TR and is connected to a write line WR. The other source/drain region 15B of the selection transistor TR is connected to a select line SL. The other end of the nonvolatile memory element 50 is connected to a bit line BL.

Abstract: A semiconductor device capable of efficiently increasing a capacity of a mounted storage element while achieving space saving, and an electronic apparatus including this semiconductor device are provided. The semiconductor device includes a storage element including a filament that has a first conductive layer, a second conductive layer, and an insulation layer. The first conductive layer and the second conductive layer are stacked with at least the insulation layer interposed between the first conductive layer and the second conductive layer. The filament obtains at least three identifiable resistance states by changing a combination of a state of the first conductive layer, a state of the second conductive layer, and a state of the insulation layer. The semiconductor device further includes a writing unit that produces the at least three identifiable resistance states by applying a blow current to the storage element.

Abstract: A semiconductor device of the present disclosure includes: a first gate electrode that includes a first main line section and one or a plurality of first sub line sections, in which the first main line section extends in a first direction in a first active region of a semiconductor substrate, and segments the first active region into a first region and a second region, and the one or the plurality of first sub line sections extends from the first main line section in a second direction intersecting the first direction in the first region, and segments the first region into a plurality of sub regions including a first sub region and a second sub region; a first memory element that includes a first terminal, and a second terminal coupled to the first sub region of the semiconductor substrate, and is configured to be set in a first resistive state or a second resistive state; and a second memory element that includes a first terminal, and a second terminal coupled to the second sub region of the semiconductor su

Abstract: [Object] To provide a novel examination method for a cancer treatment effect, screening method fora peptide fora cancer vaccine, and peptide and composition for inducing an immune response against cancer. [Solving Means] Provided are an examination method for a cancer treatment effect and a screening method for a peptide for a cancer vaccine each including detecting an antibody against a cancer/testis antigen or an anti-p53 antibody in a sample. It is suitable that an anti-XAGE1 antibody (IgG and/or IgA) be detected, or an anti-NY-ESO-1 antibody (IgG) be detected. Also provided are a novel peptide and novel composition for inducing immune responses against cancer.

Abstract: A semiconductor device of the present disclosure includes: a first gate electrode that includes a first main line section and one or a plurality of first sub line sections, in which the first main line section extends in a first direction in a first active region of a semiconductor substrate, and segments the first active region into a first region and a second region, and the one or the plurality of first sub line sections extends from the first main line section in a second direction intersecting the first direction in the first region, and segments the first region into a plurality of sub regions including a first sub region and a second sub region; a first memory element that includes a first terminal, and a second terminal coupled to the first sub region of the semiconductor substrate, and is configured to be set in a first resistive state or a second resistive state; and a second memory element that includes a first terminal, and a second terminal coupled to the second sub region of the semiconductor su

Abstract: The present disclosure relates to a semiconductor storage device, a driving method, and an electronic device capable of suppressing a layout area and improving reliability. A semiconductor storage device is provided with one or more selection transistors, a resistance change element one end of which is connected to a bit line and the other end of which is connected to a drain terminal of a selection transistor, the resistance change element a resistance value of which changes by a current of a predetermined value or larger allowed to flow, and a write control unit connected to a connection point between the selection transistor and the resistance change element and controls the current flowing through the resistance change element when data is written in the resistance change element. The present technology is applicable to, for example, a non-volatile memory provided with a storage element configured by a magnetic tunnel junction.

Abstract: An object of the present technology is to improve the performance of a memory cell that stores the value reflecting the direction of an electric current. The memory cell includes an N-type transistor, a P-type transistor, and a storage element. The N-type transistor supplies a current either from a source to a drain thereof or from the drain to the source. The P-type transistor supplies a current from a source to a drain thereof. The storage element stores a logical value reflecting the direction of the current supplied from the drain of the N-type transistor and from the drain of the P-type transistor.

Abstract: The present disclosure relates to a semiconductor storage device, a driving method, and an electronic device capable of suppressing a layout area and improving reliability. A semiconductor storage device is provided with one or more selection transistors, a resistance change element one end of which is connected to a bit line and the other end of which is connected to a drain terminal of a selection transistor, the resistance change element a resistance value of which changes by a current of a predetermined value or larger allowed to flow, and a write control unit connected to a connection point between the selection transistor and the resistance change element and controls the current flowing through the resistance change element when data is written in the resistance change element. The present technology is applicable to, for example, a non-volatile memory provided with a storage element configured by a magnetic tunnel junction.

Abstract: An object of the present technology is to improve the performance of a memory cell that stores the value reflecting the direction of an electric current. The memory cell includes an N-type transistor, a P-type transistor, and a storage element. The N-type transistor supplies a current either from a source to a drain thereof or from the drain to the source. The P-type transistor supplies a current from a source to a drain thereof. The storage element stores a logical value reflecting the direction of the current supplied from the drain of the N-type transistor and from the drain of the P-type transistor.

Abstract: A mask pattern design method includes: dividing design layout data for a pattern into multiple regions and extracting any region wherein transfer dimensions obtained from a transfer simulation of the pattern from the plurality of regions exceeds a predetermined allowance range; setting a process window of which multiple transfer conditions of the pattern data from the region extracted by the process are each changed, and computing transfer dimensions obtained from a transfer simulation with each transfer condition with the process window; and extracting the transfer conditions wherein the transfer dimension obtained from the transfer simulation with each transfer condition with the process window exceeds a predetermined allowance range, and computing yield from an occurrence probability regarding the transfer condition.

Abstract: A pattern correction method includes: a correction step of performing pattern correction on a semiconductor circuit pattern having plural transistors as component elements; an order of priority recognition step of recognizing an order of priority set with respect to the plural transistors prior to the pattern correction at the correction step; and a condition adjustment step of adjusting correction conditions for the pattern correction with reference to the transistor having a high priority recognized at the order of priority recognition step in the pattern correction at the correction step.

Abstract: A pattern correction method includes: a correction step of performing pattern correction on a semiconductor circuit pattern having plural transistors as component elements; an order of priority recognition step of recognizing an order of priority set with respect to the plural transistors prior to the pattern correction at the correction step; and a condition adjustment step of adjusting correction conditions for the pattern correction with reference to the transistor having a high priority recognized at the order of priority recognition step in the pattern correction at the correction step.

Abstract: A mask pattern design method includes: dividing design layout data for a pattern into multiple regions and extracting any region wherein transfer dimensions obtained from a transfer simulation of the pattern from the plurality of regions exceeds a predetermined allowance range; setting a process window of which multiple transfer conditions of the pattern data from the region extracted by the process are each changed, and computing transfer dimensions obtained from a transfer simulation with each transfer condition with the process window; and extracting the transfer conditions wherein the transfer dimension obtained from the transfer simulation with each transfer condition with the process window exceeds a predetermined allowance range, and computing yield from an occurrence probability regarding the transfer condition.

Abstract: When a plug is to be fitted to a first connector from one side and a plug is to be fitted to a second connector from the other side of an optical coupling device, the first connector and the second connector shift in an X direction to ease stresses working on an internal optical fiber. Therefore, stresses working on the optical fiber can be eased without having to extend a length of the internal fiber, and accordingly it is made possible to reduce an overall size of the optical coupling device.

Abstract: When a plug is to be fitted to a first connector from one side and a plug is to be fitted to a second connector from the other side of an optical coupling device, the first connector and the second connector shift in an X direction to ease stresses working on an internal optical fiber. Therefore, stresses working on the optical fiber can be eased without having to extend a length of the internal fiber, and accordingly it is made possible to reduce an overall size of the optical coupling device.

Abstract: In the magnetic recording/regenerating apparatus of the present invention, the linking member R expands, contracts and rotates under the effect of the elastic member 9d by causing sliding with a slight force by pressing the pressing section of the first member of the second sliding member S. The rotation permits discharge of the loaded cartridge and easy ejection of the cartridge with a slight force.