Abstract: The invention relates to a process for producing a brominated trifluoromethylbenzene represented by the general formula (1). This process includes brominating in a liquid or gas phase a trifluoromethylbenzene, represented by the general formula (2), by bromine in the presence of a catalyst under a condition that the bromine is coexistent with chlorine, where n is an integer of 1-2, and m is an integer of 1-3 where n is an integer of 1-2. The catalyst is preferably iron chloride in the case of the bromination in a liquid phase. It is preferably activated carbon carrying thereon iron chloride in the case of the bromination in a gas phase. The trifluoromethylbenzene is turned to the brominated trifluoromethylbenzene with high reactivity and high yield.

Abstract: A process for producing a binaphthol bistriflate, 2,2′-bis(trifluoromethanesulfonyloxy)-1,1′-binaphthyl, includes reacting 1,1′-bi-2-naphthol with trifluoromethanesulfonyl fluoride, in a polar solvent, in the presence of an organic base. The reaction proceeds quickly at a low temperature by using a polar solvent as the reaction solvent, while the reaction pressure does not become high. The polar solvent is preferably at least one selected from N,N-dimethylformamide, N,N-dimethylacetoamide, 1-methyl-2-pyrrolidinone, and acetonitrile.

Abstract: The invention relates to a method for producing a first perhalogenated cyclopentene represented by the general formula: C5ClBF8−B where B is an integer of from 0 to 7. The method includes a step of (a) fluorinating a second perhalogenated cyclopentene by hydrogen fluoride in a gas phase in the presence of a fluorination catalyst. The second perhalogenated cyclopentene is represented by general formula: C5ClAF8−A where A is an integer of from 1 to 8, and A is not smaller than B. With this method, the first perhalogenated cyclopentene (e.g., 1,2-dichloro-3,3,4,4,5,5-hexafluorocyclopentene, another chlorofluorinated cyclopentene, or octafluorocyclopentene) can continuously easily be produced, for example, from octachlorocyclopentene obtained by chlorination of hexachlorocyclopentadiene that is easily available. Therefore, the above method is very useful as an industrial scale production method.

Abstract: The present invention relates to a synchronizing signal generation circuit equipped with a PLL circuit. A pulse signal having a time constant that is broader than the clock width of a horizontal synchronizing signal included within synchronizing signals and that moreover contains steady-state phase error of the PLL circuit is generated and inputted to a phase comparison inhibiting circuit by way of a signal conversion circuit. The logic level of the pulse signal is then varied for the active interval and the inactive interval of the vertical synchronizing signal, phase comparison of the horizontal synchronizing signal and the reproduced horizontal synchronizing signal being inhibited during the active interval. The reproduced horizontal synchronizing signal is generated based on the output of two frequency dividers.

Abstract: In a satellite communications system, a unique word is transmitted from a central station at frame intervals to the satellite and broadcast to terminal stations. Blocks of data from the central station are composed into packets which are exclusively encrypted, and asynchronously transmitted to the satellite by giving priority to the unique word by interrupting the transmission of packets. A copy of data signals from the central-station data terminals is stored and retransmitted to a terminal station in response to a repeat request signal received therefrom. In each terminal station, the unique word is detected to generate a timing signal in response to which the encrypted packet is deciphered. The deciphered packets are decomposed into blocks of data, and sent to a destination data terminal.

Abstract: A microprocessor system includes interstage buffer circuits and a slave system. The interstage buffer circuits include data signal buffer circuits (8a, 8b) and a swap buffer circuit (9), connected in parallel with the data signal buffer circuits (8a, 8b), for performing bit width conversion. The slave system is connected to a bus for connecting an interstage control signal buffer circuit and an interface control signal buffer circuits, a bus for connecting an interstage address signal buffer circuit and an interface address signal buffer circuit, and a bus for connecting the buffer circuits (8a, 9, 8b) and an interface data signal buffer circuit.

Abstract: Equipment for testing a digital satellite communication system in which multiple digital satellite communication terminals are interconnectable over multiple channels. The equipment includes a single satellite delay simulator intervening between transmit communication terminals and receive communication terminals. The delay simulator is implemented by a satellite delay circuit accommodating multiple channels, and clock matching circuits each being connected to the output or the input of the delay circuit, whereby the communication terminals are individually connectable to the delay circuit via the clock matching circuits. With this configuration, the equipment tests the system by applying a satellite delay simulation to all of the communication terminals, which are operating on independent clocks, at the same time and by using a single satellite delay simulator.

Abstract: In order to process data transmitted from a plurality of earth stations in a TDMA communications system with high speed, the data transmitted chronologically over a multiframe and written into a first memory according to first discriminating signals in a manner as to be grouped with respect to the earth stations, are then read out from the first memory according to second discriminating signals stored in a second memory irrespective of the received order. The data read out from the first memory are arranged in a manner as to be processed with ease in the subsequent unit.

Abstract: A terminal control device for a reference station in a TDMA satellite communication system includes means for generating a parallel acquisition window applicable to a parallel initial acquisition system and a sequential acquisition window applicable to a sequential initial acquisition system each in a TDMA frame, and selector means for selecting either one of the two different kinds of windows. The device selectively uses the two different acquisition systems and, thereby, accomplishes the advantages of both of the systems at the same time, i.e. short terminal buildup time and high TDMA frame utilization efficiency.