Patents by Inventor Mikito Sakakibara

Mikito Sakakibara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9735142
    Abstract: With a microwave FET, an incorporated Schottky junction capacitance or PN junction capacitance is small and such a junction is weak against static electricity. However, with a microwave device, the method of connecting a protecting diode cannot be used since this method increases the parasitic capacitance and causes degradation of the high-frequency characteristics. In order to solve the above problems, a protecting element, having a first n+-type region—insulating region—second n+-type region arrangement is connected in parallel between two terminals of a protected element having a PN junction, Schottky junction, or capacitor. Since discharge can be performed between the first and second n+ regions that are adjacent each other, electrostatic energy that would reach the operating region of an FET can be attenuated without increasing the parasitic capacitance.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: August 15, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Tetsuro Asano, Mikito Sakakibara, Toshikazu Hirai
  • Publication number: 20140225227
    Abstract: With a microwave FET, an incorporated Schottky junction capacitance or PN junction capacitance is small and such a junction is weak against static electricity. However, with a microwave device, the method of connecting a protecting diode cannot be used since this method increases the parasitic capacitance and causes degradation of the high-frequency characteristics. In order to solve the above problems, a protecting element, having a first n+-type region—insulating region—second n+-type region arrangement is connected in parallel between two terminals of a protected element having a PN junction, Schottky junction, or capacitor. Since discharge can be performed between the first and second n+ regions that are adjacent each other, electrostatic energy that would reach the operating region of an FET can be attenuated without increasing the parasitic capacitance.
    Type: Application
    Filed: April 15, 2014
    Publication date: August 14, 2014
    Applicant: Semiconductor Components Industries, LLC
    Inventors: Tetsuro Asano, Mikito Sakakibara, Toshikazu Hirai
  • Patent number: 8742506
    Abstract: With a microwave FET, an incorporated Schottky junction capacitance or PN junction capacitance is small and such a junction is weak against static electricity. However, with a microwave device, the method of connecting a protecting diode cannot be used since this method increases the parasitic capacitance and causes degradation of the high-frequency characteristics. In order to solve the above problems, a protecting element, having a first n+-type region-insulating region-second n+-type region arrangement is connected in parallel between two terminals of a protected element having a PN junction, Schottky junction, or capacitor. Since discharge can be performed between the first and second n+ regions that are adjacent each other, electrostatic energy that would reach the operating region of an FET can be attenuated without increasing the parasitic capacitance.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: June 3, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Tetsuro Asano, Mikito Sakakibara, Toshikazu Hirai
  • Patent number: 8450805
    Abstract: A high-resistance element is connected as a part of a control resistor between a control terminal pad and a protecting element, immediately near the control terminal pad. Thus, even if a high-frequency analog signal leaks to the control resistor, the leaked signal is attenuated by the high-resistance element. This substantially eliminates the possibility of the high-frequency analog signal transmitting to the control terminal pad. Accordingly, an increase in insertion loss can be suppressed.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: May 28, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Tetsuro Asano, Mikito Sakakibara
  • Publication number: 20120228738
    Abstract: With a microwave FET, an incorporated Schottky junction capacitance or PN junction capacitance is small and such a junction is weak against static electricity. However, with a microwave device, the method of connecting a protecting diode cannot be used since this method increases the parasitic capacitance and causes degradation of the high-frequency characteristics. In order to solve the above problems, a protecting element, having a first n+-type region-insulating region-second n+-type region arrangement is connected in parallel between two terminals of a protected element having a PN junction, Schottky junction, or capacitor. Since discharge can be performed between the first and second n+ regions that are adjacent each other, electrostatic energy that would reach the operating region of an FET can be attenuated without increasing the parasitic capacitance.
    Type: Application
    Filed: May 18, 2012
    Publication date: September 13, 2012
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro ASANO, Mikito SAKAKIBARA, Toshikazu HIRAI
  • Patent number: 7732868
    Abstract: A protecting element, comprising a first n+-type region, an insulating region, and a second n+-type region, is connected in parallel between two terminals of an FET. Since discharge across the first and second n+ regions is enabled, electrostatic energy that reaches the operating region of the FET can be attenuated without increasing the parasitic capacitance.
    Type: Grant
    Filed: November 28, 2002
    Date of Patent: June 8, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Asano, Mikito Sakakibara, Toshikazu Hirai
  • Patent number: 7701032
    Abstract: A separation element formed of one of a conduction region and a metal layer is placed between two elements in proximity to each other. The separation element is connected to a high resistance element and to a direct current terminal pad. A connection route extending from the direct current terminal pad to the separation element is a route in which a potential does not vibrate with high frequency. This results in a placement of a high frequency GND potential between the two elements, at least one of which is subjected to transmitting the high frequency signals, whereby leak of the high frequency signals can be prevented between the two elements.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: April 20, 2010
    Assignee: SANYO Electric Co., Ltd.
    Inventors: Tetsuro Asano, Yuichi Kusaka, Mikito Sakakibara
  • Patent number: 7498616
    Abstract: A gate wiring electrode is formed into a ladder-like pattern. Moreover, between source electrodes and drain electrodes in the entire Switch MMIC, the gate wiring electrodes are disposed. Furthermore, at a cross part between the gate wiring electrode and the source electrode or the drain electrode, a nitride film having a large relative dielectric constant and a polyimide or a hollow part having a small relative dielectric constant are disposed. Accordingly, a capacitance at the cross part is reduced. Thus, a second harmonic wave level can be lowered. Moreover, a leak of a high-frequency signal between the drain electrode and the source electrode can be prevented. Thus, a third harmonic level can be lowered. Consequently, distortion characteristics of the Switch MMIC can be significantly improved.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: March 3, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Asano, Mikito Sakakibara, Yuichi Kusaka, Hidetoshi Ishihara
  • Patent number: 7358788
    Abstract: Protecting elements are respectively connected between a control terminal Ctl and a ground terminal GND of a logic circuit L, between a point Cp and a ground terminal GND, and between a power supply terminal VDD and a ground terminal GND thereof. With this, an E-FET, constituting an inverter 70, and capacitors Ci and Cr can be protected from electrostatic breakdown due to external static electricity. Since the protecting element can be constituted by requisite components for the logic circuit, an additional step or structure is not especially required to provide the protecting element.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: April 15, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Asano, Yuichi Kusaka, Mikito Sakakibara, Hidetoshi Ishihara
  • Patent number: 7339210
    Abstract: High resistance elements of 5 K? or more are connected near first and second control terminals between the first and second control terminals and respective crossing portion of first and second connectings. Even when a high frequency analog signal transmitted in a pad wire leaks to the first and second connectings, the high frequency analog signal is attenuated by the high resistance elements. Accordingly, the high frequency analog signal is not substantially transmitted to control terminal pads. It is therefore possible to suppress an increase in insertion loss.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: March 4, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Asano, Mikito Sakakibara
  • Patent number: 7262470
    Abstract: With a microwave FET, the internalized Schottky junction capacitance or pn junction capacitance is small and these junctions are weak against static electricity. However, with a microwave device, a protecting diode could not be connected since the increase of parasitic capacitance resulting from this method causes degradation of the high frequency characteristics. Therefore, to eliminate this problem, a semiconductor device is provided, wherein two paths, extending from a gate electrode pad to a gate electrode on an operating region, are arranged, with one path running near a source electrode pad, the other path running near a drain electrode pad, and at the respective parts where a path becomes close to a pad, the abovementioned protecting elements are connected between the gate electrode and source electrode and between the gate electrode and drain electrode to improve the electrostatic breakdown voltage of the FET from approximately 100V to 700V.
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: August 28, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Asano, Mikito Sakakibara, Toshikazu Hiraj
  • Publication number: 20060289963
    Abstract: A separation element formed of one of a conduction region and a metal layer is placed between two elements in proximity to each other. The separation element is connected to a high resistance element and to a direct current terminal pad. A connection route extending from the direct current terminal pad to the separation element is a route in which a potential does not vibrate with high frequency. This results in a placement of a high frequency GND potential between the two elements, at least one of which is subjected to transmitting the high frequency signals, whereby leak of the high frequency signals can be prevented between the two elements.
    Type: Application
    Filed: May 30, 2006
    Publication date: December 28, 2006
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Tetsuro Asano, Yuichi Kusaka, Mikito Sakakibara
  • Publication number: 20060255403
    Abstract: A gate wiring electrode is formed into a ladder-like pattern. Moreover, between source electrodes and drain electrodes in the entire Switch MMIC, the gate wiring electrodes are disposed. Furthermore, at a cross part between the gate wiring electrode and the source electrode or the drain electrode, a nitride film having a large relative dielectric constant and a polyimide or a hollow part having a small relative dielectric constant are disposed. Accordingly, a capacitance at the cross part is reduced. Thus, a second harmonic wave level can be lowered. Moreover, a leak of a high-frequency signal between the drain electrode and the source electrode can be prevented. Thus, a third harmonic level can be lowered. Consequently, distortion characteristics of the Switch MMIC can be significantly improved.
    Type: Application
    Filed: April 27, 2006
    Publication date: November 16, 2006
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Tetsuro Asano, Mikito Sakakibara, Yuichi Kusaka, Hidetoshi Ishihara
  • Publication number: 20060252651
    Abstract: Protecting elements are respectively connected between a control terminal Ctl and a ground terminal GND of a logic circuit L, between a point Cp and a ground terminal GND, and between a power supply terminal VDD and a ground terminal GND thereof. With this, an E-FET, constituting an inverter 70, and capacitors Ci and Cr can be protected from electrostatic breakdown due to external static electricity. Since the protecting element can be constituted by requisite components for the logic circuit, an additional step or structure is not especially required to provide the protecting element.
    Type: Application
    Filed: April 27, 2006
    Publication date: November 9, 2006
    Applicant: SANYO ELECTRIC CO., LTD
    Inventors: Tetsuro Asano, Yuichi Kusaka, Mikito Sakakibara, Hidetoshi Ishihara
  • Publication number: 20060177077
    Abstract: A high frequency mixer circuit is used as a down converter in which an RF signal and an LO signal are mixed to generate an IF signal, or as an up converter in which an IF signal and an LO signal are mixed to generate an RF signal. The high frequency mixer circuit has a wiring layout wherein wiring lines for propagating LO signals intersect only one of the wiring lines for propagating RF signals or IF signals.
    Type: Application
    Filed: February 9, 2006
    Publication date: August 10, 2006
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Yasuyuki Okada, Akihito Nagamatsu, Katsuaki Onoda, Shigehiro Nakamura, Mikito Sakakibara
  • Publication number: 20060163659
    Abstract: A high-resistance element is connected as a part of a control resistor between a control terminal pad and a protecting element, immediately near the control terminal pad. Thus, even if a high-frequency analog signal leaks to the control resistor, the leaked signal is attenuated by the high-resistance element. This substantially eliminates the possibility of the high-frequency analog signal transmitting to the control terminal pad. Accordingly, an increase in insertion loss can be suppressed.
    Type: Application
    Filed: December 22, 2005
    Publication date: July 27, 2006
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Tetsuro Asano, Mikito Sakakibara
  • Publication number: 20060163609
    Abstract: High resistance elements of 5 K? or more are connected near first and second control terminals between the first and second control terminals and respective crossing portion of first and second connectings. Even when a high frequency analog signal transmitted in a pad wire leaks to the first and second connectings, the high frequency analog signal is attenuated by the high resistance elements. Accordingly, the high frequency analog signal is not substantially transmitted to control terminal pads. It is therefore possible to suppress an increase in insertion loss.
    Type: Application
    Filed: December 22, 2005
    Publication date: July 27, 2006
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Tetsuro Asano, Mikito Sakakibara
  • Publication number: 20060151816
    Abstract: A protecting element, comprising a first n+-type region, an insulating region, and a second n+-type region, is connected in parallel between two terminals of an FET. Since discharge across the first and second n+ regions is enabled, electrostatic energy that reaches the operating region of the FET can be attenuated without increasing the parasitic capacitance.
    Type: Application
    Filed: November 28, 2002
    Publication date: July 13, 2006
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Asano, Mikito Sakakibara, Toshikazu Hirai
  • Patent number: 7005688
    Abstract: A semiconductor switching device includes a plurality of metal layers. At least one of the metal layers forming a Schottky junction with a semi-insulating substrate or an insulating layer on a substrate. The device also includes an impurity diffusion region, and a high-concentration impurity region formed between two of the metal layers or between one of the metal layers and the impurity diffusion region so as to suppress expansion of a depletion layer from the corresponding metal layer.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: February 28, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Asano, Mikito Sakakibara, Yoshibumi Nakajima, Hidetoshi Ishihara
  • Patent number: 6946891
    Abstract: Since improvement measures are not taken in regard to the electrostatic breakdown voltage, electrostatic breakdown voltages, between the common input terminal IN—first control terminal Ctl-1, between the common input terminal IN—second control terminal Ctl-2, between the first control terminal Ctl-1—the first output terminal OUT1, and between the second control terminal Ctl-2—the second output terminal OUT2, where both ends of gate Schottky junctions of FETs are lead out to the exterior, are low. To solve the problem, the embodiment of the invention provides a switch circuit device, wherein protecting elements are connected by disposing two electrode pads, for connection to a single control terminal, on a chip and positioning the electrode pads near the common input terminal pad I and an output terminal pad O1 or O2.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: September 20, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuro Asano, Mikito Sakakibara, Toshikazu Hirai