Patents by Inventor Mikito Sakakibara
Mikito Sakakibara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9735142Abstract: With a microwave FET, an incorporated Schottky junction capacitance or PN junction capacitance is small and such a junction is weak against static electricity. However, with a microwave device, the method of connecting a protecting diode cannot be used since this method increases the parasitic capacitance and causes degradation of the high-frequency characteristics. In order to solve the above problems, a protecting element, having a first n+-type region—insulating region—second n+-type region arrangement is connected in parallel between two terminals of a protected element having a PN junction, Schottky junction, or capacitor. Since discharge can be performed between the first and second n+ regions that are adjacent each other, electrostatic energy that would reach the operating region of an FET can be attenuated without increasing the parasitic capacitance.Type: GrantFiled: April 15, 2014Date of Patent: August 15, 2017Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Tetsuro Asano, Mikito Sakakibara, Toshikazu Hirai
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Publication number: 20140225227Abstract: With a microwave FET, an incorporated Schottky junction capacitance or PN junction capacitance is small and such a junction is weak against static electricity. However, with a microwave device, the method of connecting a protecting diode cannot be used since this method increases the parasitic capacitance and causes degradation of the high-frequency characteristics. In order to solve the above problems, a protecting element, having a first n+-type region—insulating region—second n+-type region arrangement is connected in parallel between two terminals of a protected element having a PN junction, Schottky junction, or capacitor. Since discharge can be performed between the first and second n+ regions that are adjacent each other, electrostatic energy that would reach the operating region of an FET can be attenuated without increasing the parasitic capacitance.Type: ApplicationFiled: April 15, 2014Publication date: August 14, 2014Applicant: Semiconductor Components Industries, LLCInventors: Tetsuro Asano, Mikito Sakakibara, Toshikazu Hirai
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Patent number: 8742506Abstract: With a microwave FET, an incorporated Schottky junction capacitance or PN junction capacitance is small and such a junction is weak against static electricity. However, with a microwave device, the method of connecting a protecting diode cannot be used since this method increases the parasitic capacitance and causes degradation of the high-frequency characteristics. In order to solve the above problems, a protecting element, having a first n+-type region-insulating region-second n+-type region arrangement is connected in parallel between two terminals of a protected element having a PN junction, Schottky junction, or capacitor. Since discharge can be performed between the first and second n+ regions that are adjacent each other, electrostatic energy that would reach the operating region of an FET can be attenuated without increasing the parasitic capacitance.Type: GrantFiled: May 18, 2012Date of Patent: June 3, 2014Assignee: Semiconductor Components Industries, LLCInventors: Tetsuro Asano, Mikito Sakakibara, Toshikazu Hirai
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Patent number: 8450805Abstract: A high-resistance element is connected as a part of a control resistor between a control terminal pad and a protecting element, immediately near the control terminal pad. Thus, even if a high-frequency analog signal leaks to the control resistor, the leaked signal is attenuated by the high-resistance element. This substantially eliminates the possibility of the high-frequency analog signal transmitting to the control terminal pad. Accordingly, an increase in insertion loss can be suppressed.Type: GrantFiled: December 22, 2005Date of Patent: May 28, 2013Assignee: Semiconductor Components Industries, LLCInventors: Tetsuro Asano, Mikito Sakakibara
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Publication number: 20120228738Abstract: With a microwave FET, an incorporated Schottky junction capacitance or PN junction capacitance is small and such a junction is weak against static electricity. However, with a microwave device, the method of connecting a protecting diode cannot be used since this method increases the parasitic capacitance and causes degradation of the high-frequency characteristics. In order to solve the above problems, a protecting element, having a first n+-type region-insulating region-second n+-type region arrangement is connected in parallel between two terminals of a protected element having a PN junction, Schottky junction, or capacitor. Since discharge can be performed between the first and second n+ regions that are adjacent each other, electrostatic energy that would reach the operating region of an FET can be attenuated without increasing the parasitic capacitance.Type: ApplicationFiled: May 18, 2012Publication date: September 13, 2012Applicant: Sanyo Electric Co., Ltd.Inventors: Tetsuro ASANO, Mikito SAKAKIBARA, Toshikazu HIRAI
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Patent number: 7732868Abstract: A protecting element, comprising a first n+-type region, an insulating region, and a second n+-type region, is connected in parallel between two terminals of an FET. Since discharge across the first and second n+ regions is enabled, electrostatic energy that reaches the operating region of the FET can be attenuated without increasing the parasitic capacitance.Type: GrantFiled: November 28, 2002Date of Patent: June 8, 2010Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Mikito Sakakibara, Toshikazu Hirai
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Patent number: 7701032Abstract: A separation element formed of one of a conduction region and a metal layer is placed between two elements in proximity to each other. The separation element is connected to a high resistance element and to a direct current terminal pad. A connection route extending from the direct current terminal pad to the separation element is a route in which a potential does not vibrate with high frequency. This results in a placement of a high frequency GND potential between the two elements, at least one of which is subjected to transmitting the high frequency signals, whereby leak of the high frequency signals can be prevented between the two elements.Type: GrantFiled: May 30, 2006Date of Patent: April 20, 2010Assignee: SANYO Electric Co., Ltd.Inventors: Tetsuro Asano, Yuichi Kusaka, Mikito Sakakibara
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Patent number: 7498616Abstract: A gate wiring electrode is formed into a ladder-like pattern. Moreover, between source electrodes and drain electrodes in the entire Switch MMIC, the gate wiring electrodes are disposed. Furthermore, at a cross part between the gate wiring electrode and the source electrode or the drain electrode, a nitride film having a large relative dielectric constant and a polyimide or a hollow part having a small relative dielectric constant are disposed. Accordingly, a capacitance at the cross part is reduced. Thus, a second harmonic wave level can be lowered. Moreover, a leak of a high-frequency signal between the drain electrode and the source electrode can be prevented. Thus, a third harmonic level can be lowered. Consequently, distortion characteristics of the Switch MMIC can be significantly improved.Type: GrantFiled: April 27, 2006Date of Patent: March 3, 2009Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Mikito Sakakibara, Yuichi Kusaka, Hidetoshi Ishihara
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Patent number: 7358788Abstract: Protecting elements are respectively connected between a control terminal Ctl and a ground terminal GND of a logic circuit L, between a point Cp and a ground terminal GND, and between a power supply terminal VDD and a ground terminal GND thereof. With this, an E-FET, constituting an inverter 70, and capacitors Ci and Cr can be protected from electrostatic breakdown due to external static electricity. Since the protecting element can be constituted by requisite components for the logic circuit, an additional step or structure is not especially required to provide the protecting element.Type: GrantFiled: April 27, 2006Date of Patent: April 15, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Yuichi Kusaka, Mikito Sakakibara, Hidetoshi Ishihara
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Patent number: 7339210Abstract: High resistance elements of 5 K? or more are connected near first and second control terminals between the first and second control terminals and respective crossing portion of first and second connectings. Even when a high frequency analog signal transmitted in a pad wire leaks to the first and second connectings, the high frequency analog signal is attenuated by the high resistance elements. Accordingly, the high frequency analog signal is not substantially transmitted to control terminal pads. It is therefore possible to suppress an increase in insertion loss.Type: GrantFiled: December 22, 2005Date of Patent: March 4, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Mikito Sakakibara
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Patent number: 7262470Abstract: With a microwave FET, the internalized Schottky junction capacitance or pn junction capacitance is small and these junctions are weak against static electricity. However, with a microwave device, a protecting diode could not be connected since the increase of parasitic capacitance resulting from this method causes degradation of the high frequency characteristics. Therefore, to eliminate this problem, a semiconductor device is provided, wherein two paths, extending from a gate electrode pad to a gate electrode on an operating region, are arranged, with one path running near a source electrode pad, the other path running near a drain electrode pad, and at the respective parts where a path becomes close to a pad, the abovementioned protecting elements are connected between the gate electrode and source electrode and between the gate electrode and drain electrode to improve the electrostatic breakdown voltage of the FET from approximately 100V to 700V.Type: GrantFiled: February 6, 2004Date of Patent: August 28, 2007Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Mikito Sakakibara, Toshikazu Hiraj
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Publication number: 20060289963Abstract: A separation element formed of one of a conduction region and a metal layer is placed between two elements in proximity to each other. The separation element is connected to a high resistance element and to a direct current terminal pad. A connection route extending from the direct current terminal pad to the separation element is a route in which a potential does not vibrate with high frequency. This results in a placement of a high frequency GND potential between the two elements, at least one of which is subjected to transmitting the high frequency signals, whereby leak of the high frequency signals can be prevented between the two elements.Type: ApplicationFiled: May 30, 2006Publication date: December 28, 2006Applicant: SANYO ELECTRIC CO., LTD.Inventors: Tetsuro Asano, Yuichi Kusaka, Mikito Sakakibara
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Publication number: 20060255403Abstract: A gate wiring electrode is formed into a ladder-like pattern. Moreover, between source electrodes and drain electrodes in the entire Switch MMIC, the gate wiring electrodes are disposed. Furthermore, at a cross part between the gate wiring electrode and the source electrode or the drain electrode, a nitride film having a large relative dielectric constant and a polyimide or a hollow part having a small relative dielectric constant are disposed. Accordingly, a capacitance at the cross part is reduced. Thus, a second harmonic wave level can be lowered. Moreover, a leak of a high-frequency signal between the drain electrode and the source electrode can be prevented. Thus, a third harmonic level can be lowered. Consequently, distortion characteristics of the Switch MMIC can be significantly improved.Type: ApplicationFiled: April 27, 2006Publication date: November 16, 2006Applicant: SANYO ELECTRIC CO., LTD.Inventors: Tetsuro Asano, Mikito Sakakibara, Yuichi Kusaka, Hidetoshi Ishihara
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Publication number: 20060252651Abstract: Protecting elements are respectively connected between a control terminal Ctl and a ground terminal GND of a logic circuit L, between a point Cp and a ground terminal GND, and between a power supply terminal VDD and a ground terminal GND thereof. With this, an E-FET, constituting an inverter 70, and capacitors Ci and Cr can be protected from electrostatic breakdown due to external static electricity. Since the protecting element can be constituted by requisite components for the logic circuit, an additional step or structure is not especially required to provide the protecting element.Type: ApplicationFiled: April 27, 2006Publication date: November 9, 2006Applicant: SANYO ELECTRIC CO., LTDInventors: Tetsuro Asano, Yuichi Kusaka, Mikito Sakakibara, Hidetoshi Ishihara
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Publication number: 20060177077Abstract: A high frequency mixer circuit is used as a down converter in which an RF signal and an LO signal are mixed to generate an IF signal, or as an up converter in which an IF signal and an LO signal are mixed to generate an RF signal. The high frequency mixer circuit has a wiring layout wherein wiring lines for propagating LO signals intersect only one of the wiring lines for propagating RF signals or IF signals.Type: ApplicationFiled: February 9, 2006Publication date: August 10, 2006Applicant: Sanyo Electric Co., Ltd.Inventors: Yasuyuki Okada, Akihito Nagamatsu, Katsuaki Onoda, Shigehiro Nakamura, Mikito Sakakibara
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Publication number: 20060163659Abstract: A high-resistance element is connected as a part of a control resistor between a control terminal pad and a protecting element, immediately near the control terminal pad. Thus, even if a high-frequency analog signal leaks to the control resistor, the leaked signal is attenuated by the high-resistance element. This substantially eliminates the possibility of the high-frequency analog signal transmitting to the control terminal pad. Accordingly, an increase in insertion loss can be suppressed.Type: ApplicationFiled: December 22, 2005Publication date: July 27, 2006Applicant: SANYO ELECTRIC CO., LTD.Inventors: Tetsuro Asano, Mikito Sakakibara
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Publication number: 20060163609Abstract: High resistance elements of 5 K? or more are connected near first and second control terminals between the first and second control terminals and respective crossing portion of first and second connectings. Even when a high frequency analog signal transmitted in a pad wire leaks to the first and second connectings, the high frequency analog signal is attenuated by the high resistance elements. Accordingly, the high frequency analog signal is not substantially transmitted to control terminal pads. It is therefore possible to suppress an increase in insertion loss.Type: ApplicationFiled: December 22, 2005Publication date: July 27, 2006Applicant: SANYO ELECTRIC CO., LTD.Inventors: Tetsuro Asano, Mikito Sakakibara
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Publication number: 20060151816Abstract: A protecting element, comprising a first n+-type region, an insulating region, and a second n+-type region, is connected in parallel between two terminals of an FET. Since discharge across the first and second n+ regions is enabled, electrostatic energy that reaches the operating region of the FET can be attenuated without increasing the parasitic capacitance.Type: ApplicationFiled: November 28, 2002Publication date: July 13, 2006Applicant: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Mikito Sakakibara, Toshikazu Hirai
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Patent number: 7005688Abstract: A semiconductor switching device includes a plurality of metal layers. At least one of the metal layers forming a Schottky junction with a semi-insulating substrate or an insulating layer on a substrate. The device also includes an impurity diffusion region, and a high-concentration impurity region formed between two of the metal layers or between one of the metal layers and the impurity diffusion region so as to suppress expansion of a depletion layer from the corresponding metal layer.Type: GrantFiled: October 14, 2003Date of Patent: February 28, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Mikito Sakakibara, Yoshibumi Nakajima, Hidetoshi Ishihara
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Patent number: 6946891Abstract: Since improvement measures are not taken in regard to the electrostatic breakdown voltage, electrostatic breakdown voltages, between the common input terminal IN—first control terminal Ctl-1, between the common input terminal IN—second control terminal Ctl-2, between the first control terminal Ctl-1—the first output terminal OUT1, and between the second control terminal Ctl-2—the second output terminal OUT2, where both ends of gate Schottky junctions of FETs are lead out to the exterior, are low. To solve the problem, the embodiment of the invention provides a switch circuit device, wherein protecting elements are connected by disposing two electrode pads, for connection to a single control terminal, on a chip and positioning the electrode pads near the common input terminal pad I and an output terminal pad O1 or O2.Type: GrantFiled: February 20, 2004Date of Patent: September 20, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Mikito Sakakibara, Toshikazu Hirai