Abstract: The invention relates to transferring of a time of day value between network elements of a data transfer network. It has been surprisingly detected that the phase reference signals available to various network elements can be utilized in the synchronization of time of day values between these network elements. In the solution according to the invention, a first network element sends to a second network element a difference variable (401, 402, 403) that indicates how much the timing phase of the time of day value maintained in the first network element differs from the timing phase of the phase reference signal available to the first network element. In the second network element that receives the message, an estimate of the time of day value is formed (404, 405) based on the difference variable and the timing phase of the phase reference signal available to the second network element.

Abstract: The invention relates to a method and a system for transferring timing messages in a digital data transfer system. In a solution according to the invention a timing message is transferred (101, 102, 103) within control data carried in a protocol data unit. The timing message is dependent on a transmission moment of the protocol data unit from a network element of the digital data transfer system. The control data is a synchronization status message (Ethernet-SSM) carried in an Ethernet-frame. Therefore, the number of such protocol data units that are dedicated only for timing purposes can be reduced.

Abstract: The invention relates to a method and equipment for performing flow shaping that maintains service quality in packet-switched telecommunications. Using the method according to the invention, the speed properties (CIR, PIR, CBS) of an aggregate flow (A) can be monitored and limited in a situation, in which the aggregate flow contains delay-critical traffic (V1), the forwarding of packets representing which cannot be delayed. The invention is based on the fact that, when forwarding packets representing the aggregate flow, a variable is updated, the value of which expresses the earliest permitted moment, at which a packet, representing traffic (V2) other than the delay-critical traffic, can be forwarded. In that case, the transfer speed of the traffic (V2) other than delay-critical traffic adapts to the variations in the transfer speed of the delay-critical traffic, allowing the speed properties of the aggregate flow to be monitored and limited.

Abstract: In a system, the functionality is decentralized in a data transmission network so that the need of communications produced by and addressed to data terminals to pass by way of a single point in the data transmission network is diminished. A first data transmission installation is adapted to signal second data transmission installations, each of which is part of a ring-shaped data transmission topology, to be capable of building logical data transmission tunnels directed to the data terminals. Thereby, all the logical data transmission tunnels need not commence or, depending on the direction, terminate at the same point of a data transmission network. In addition, the data transmission installations present in a ring-shaped data transmission topology need not necessarily be taught routing information in order to enable each of these data transmission installations to send data transmission frames to be transmitted to another one of these data transmission installations.

Abstract: A device for controlling frequency synchronization includes a processor for controlling a phase-controlled clock signal to achieve phase-locking with a reference clock signal, and for controlling a frequency-controlled clock signal so as to achieve frequency-locking with the reference clock signal. The processor is also configured to monitor a deviation between the frequency and phase-controlled clock signals, detect a change of circumstances such as temperature changes causing frequency drifting of the frequency-controlled clock signal, and replace or correct the frequency-controlled clock signal with, or on the basis of, the phase-controlled clock signal when both the monitored deviation and the detected change of circumstances show correlation confirming frequency drift of the frequency-controlled clock signal.

Abstract: In a data communication system according to the invention the functionality of the gateway device is distributed in a data communication network thereby reducing the need to direct the data traffic from and to terminals (212, 213, 214) through a single point in the data communication network. A first data communication device (207) is arranged to make, through signalling, second data communication devices (204, 205, 206) capable of directing the data communications of the terminals to the starting points of the respective logical data communication tunnels (215, 216, 217). This way there is no need for all logical data communication tunnels to start from, or depending on the direction, to end at, the same point in the data communication network.

Abstract: A device for controlling a clock signal generator includes a processor (101) for forming at least two mutually different control quantities on the basis of reception moments of timing messages such as time stamps, where the reception moments are expressed as time values based on a first clock signal and the timing messages are transmitted in accordance with a second clock signal. The processor also calculates a weighted sum of the control quantities, and controls the clock signal generator with the weighted sum so as to synchronize the first clock signal and the second clock signal. The control quantities may represent, for example, a filtered value of observed phase-errors, a phase-error corresponding to a minimum observed transfer delay, and phase-errors corresponding to a given portion of the delay distribution. Using the weighted sum of the mutually different control quantities improves the utilization of the information content of the timing messages.

Abstract: A device for controlling frequency synchronization includes a processor for controlling a frequency-controlled clock signal on the basis of received timing messages so as to achieve frequency-locking between the frequency-controlled clock signal and a reference clock signal. For the purpose of finding such timing messages which have experienced similar transfer delays and thus are suitable for the frequency control, the processor is configured to control a phase-controlled clock signal on the basis of the timing messages so as to achieve phase-locking between the phase-controlled clock signal and the reference clock signal, and to select the timing messages to be used for the frequency control on the basis of phase-error indicators related to the phase control. Thus, the phase-controlled clock signal is an auxiliary clock signal that is utilized for performing the frequency control.

Abstract: A device for controlling frequency synchronization includes a processor for controlling a frequency-controlled clock signal on the basis of received timing messages so as to achieve frequency-locking between the frequency-controlled clock signal and a reference clock signal. For the purpose of finding such timing messages which have experienced similar transfer delays and thus are suitable for the frequency control, the processor is configured to control a phase-controlled clock signal on the basis of the timing messages so as to achieve phase-locking between the phase-controlled clock signal and the reference clock signal, and to select the timing messages to be used for the frequency control on the basis of phase-error indicators related to the phase control. Thus, the phase-controlled clock signal is an auxiliary clock signal that is utilized for performing the frequency control.

Abstract: The invention relates to a method and equipment for performing flow shaping that maintains service quality in packet-switched telecommunications. Using the method according to the invention, the speed properties (CIR, PIR, CBS) of an aggregate flow (A) can be monitored and limited in a situation, in which the aggregate flow contains delay-critical traffic (V1), the forwarding of packets representing which cannot be delayed. The invention is based on the fact that, when forwarding packets representing the aggregate flow, a variable is updated, the value of which expresses the earliest permitted moment, at which a packet, representing traffic (V2) other than the delay-critical traffic, can be forwarded. In that case, the transfer speed of the traffic (V2) other than delay-critical traffic adapts to the variations in the transfer speed of the delay-critical traffic, allowing the speed properties of the aggregate flow to be monitored and limited.

Abstract: A device for controlling frequency synchronization includes a processor (101) for controlling a phase-controlled clock signal to achieve phase-locking between the phase-controlled clock signal and a reference clock signal, and for controlling a frequency-controlled clock signal so as to achieve frequency-locking between the frequency-controlled clock signal and the reference clock signal. The processor is also configured to monitor a deviation between the frequency- and phase-controlled clock signals, detect a change of circumstances such as temperature changes causing frequency drifting of the frequency-controlled clock signal, and replace or correct the frequency-controlled clock signal with or on the basis of the phase-controlled clock signal when both the monitored deviation and the detected change of circumstances show correlation confirming frequency drift of the frequency-controlled clock signal.

Abstract: A method and arrangement for transferring synchronizing information in a data transmission system includes modem connections. The arrangement includes a modulator (207) arranged to generate an analog signal (222) modulated by synchronizing information, the frequency spectrum of the signal being located in a frequency range that falls outside the data transmission bands of the modem line connected to the network element. The arrangement includes a switching circuit (208) arranged to connect the analog signal to a data transmission cable (206) that forms part of the modem line connected to a network element. The arrangement includes a second switching circuit (209) arranged to receive the analog signal from a data transmission cable that forms part of the modem line connected to the second network element. The arrangement also includes a regenerator (209-arranged to regenerate the synchronizing information from the analog signal.

Abstract: A device for controlling a clock signal generator includes a processor (101) for forming at least two mutually different control quantities on the basis of reception moments of timing messages such as time stamps, where the reception moments are expressed as time values based on a first clock signal and the timing messages are transmitted in accordance with a second clock signal. The processor also calculates a weighted sum of the control quantities, and controls the clock signal generator with the weighted sum so as to synchronize the first clock signal and the second clock signal. The control quantities may represent, for example, a filtered value of observed phase-errors, a phase-error corresponding to a minimum observed transfer delay, and phase-errors corresponding to a given portion of the delay distribution. Using the weighted sum of the mutually different control quantities improves the utilization of the information content of the timing messages.

Abstract: The invention relates to a method and equipment for performing flow shaping that maintains service quality in packet-switched telecommunications. Using the method according to the invention, the speed properties (OR, PIR, CBS) of an aggregate flow (A) can be monitored and limited in a situation, in which the aggregate flow contains delay-critical traffic (V1), the forwarding of packets representing which cannot be delayed. The invention is based on the fact that, when forwarding packets representing the aggregate flow, a variable is updated, the value of which expresses the earliest permitted moment, at which a packet, representing traffic (V2) other than the delay-critical traffic, can be forwarded. In that case, the transfer speed of the traffic (V2) other than delay-critical traffic adapts to the variations in the transfer speed of the delay-critical traffic, allowing the speed properties of the aggregate flow to be monitored and limited.

Abstract: The invention relates to transmitting digital information between the network elements of a frame switched data network. In the present invention, it has surprisingly been discovered that the padding bits of the data field of a minimum sized Ethernet frame can be used for transmitting digital information between the elements of a data network. In that case the frame data field (109) of a minimum sized Ethernet frame contains an information unit (DIU), the size of which in bytes is smaller than the minimum size of a frame data field, as well as other digital information (DI) that is written in an area (107) of the frame data field that corresponds to the padding bits. The invention makes it possible to also utilize the data transmission capacity needed for transmitting the padding bits.

Abstract: A method and apparatus for monitoring and limiting the transmission speed of a data traffic flow in a situation where the traffic flow also includes delay-critical traffic. With the sending of each protocol data unit it is determined whether the sending of the next protocol data unit should be delayed in order to meet a condition set on the transmission speed. It is also determined whether the transfer speed of delay-critical traffic meets a preset condition. If the transfer speed meets the condition, delay-critical protocol data units will not be delayed but if the condition is not met, delay-critical protocol data units will be delayed just like non-delay-critical protocol data units. Thus the transfer speed of non-delay-critical traffic adapts to variations in the transfer speed of delay-critical traffic and, furthermore, the transmission speed of the traffic flow can be monitored and limited.

Abstract: The invention relates to a method and an arrangement for regenerating a timing signal in digital data communication where two network elements operate in a master/slave loop timing mode. In a solution according to the invention two different frequency difference indicators are formed. Values or changes of the values of both of them in relation to time indicate a frequency difference between a reference timing signal present in a master device and a regenerated timing signal present in a slave device. One frequency difference indicator is formed on the basis of reception taking place in the master device, and the other one on the basis of reception taking place in the slave device. The frequency of the regenerated timing signal is adjusted utilizing information contained by both frequency difference indicators. The probability of incorrect frequency adjustment measures can be thereby reduced.

Abstract: A method and system for adjusting a clock signal in a network element of a data network adjusts the clock signal based on difference values formed by received synchronizing messages. Each difference value is a difference of a reception and transmission values of a received synchronizing message. The reception value depends on a cumulated number of periods of the clock signal at a moment of arrival of the synchronizing message. The transmission value depends on a position of the synchronizing message in a chronological transmission order of synchronizing messages. When adjusting, an adjusting effect of the difference values belonging to a lower part of a margin of fluctuation of the difference values is weighted more heavily than that of an upper part. Thus, for clock signal adjustment, that share of information represented by the received synchronizing messages that has the least interference is used, irrespective of the data network load.

Abstract: A method and arrangement for adjusting the degree of filling of a jitter buffer in a network element receiving digital data. To the jitter buffer, there is connected a read-out unit for reading digital data from the jitter buffer. In the method, there is composed a time reserve indicator for the received protocol unit, the time reserve indicator being essentially the difference of an order indicator connected to the protocol unit and an order indicator connected to the operational cycle of the read-out unit. The time reserve indicator of the protocol unit indicates whether the protocol unit was received in good time, in order to ensure that the digital data is in the jitter buffer when the digital data is in turn to be read out. The degree of filling of a jitter buffer is adjusted on the basis of time reserve indicators composed for the received protocol units.

Abstract: The invention relates to determining a quantity to be measured from a communication system, such as a transmission delay or the phase difference of clock times. Measurement messages are transmitted (501, 502) between the two areas of the communication system in both transmission directions. Values of the time difference are calculated (503) for the measurement messages transmitted in at least one of the transmission directions, each of which values is the difference between the instant of reception measured at the reception and the instant of transmission measured at the transmission of the measurement message. The values of the time difference are used to calculate (504) an estimate of the distribution of the time difference, on the basis of which an estimate of the minimum value of the time difference is calculated (504).