Abstract: A transistor package includes a power transistor chip having first and second opposite sides. The first side has source, drain, and gate electrode metallizations. A multi-layer laminate substrate includes: a first structured metal layer facing the first side of the chip and electrically connected to the source electrode metallization, the drain electrode metallization, and the gate electrode metallization; a second structured metal layer having a source package terminal pad, a source sense package terminal pad, a drain package terminal pad, and a gate package terminal pad; at least one insulating layer between the structured metal layers; and vias running through the insulating layer and connecting segments of the first structured metal layer to the terminal pads of the second structured metal layer.

Abstract: A leadframe for flip chip attaching a semiconductor die thereon includes a rectangular area segmented into individual pads, the individual pads including a first pad, a second pad, and a third pad, wherein the first pad is larger than the second pad and larger than the third pad, and the second pad is located in a first corner area of the rectangular area and the third pad is located in a second corner area of the rectangular area, the second corner area being located diagonally opposite to the first corner area.

Abstract: An electronic device is disclosed. In one example, the electronic device comprises a carrier board, a metal inlay having a cavity and being arranged in the carrier board. At least one electronic component is arranged at least partially in the cavity and embedded in the carrier board. Electric contacts are located at a castellated edge of the carrier board.