Abstract: Embodiments of the disclosure provided herein include an apparatus for and method of forming an improved three-dimension (3D) memory structure/cell that includes a channel that includes polysilicon channel that has been processed to passivate and remove defects found in the channel structure of a 3D memory device, such as a 3D NAND device. In some embodiments, the processing performed on the channel structure utilizes the deposition of a fluorine containing layer that includes a concentration of fluorine (F) atoms that are then driven into a polysilicon channel layer using at least one anneal step that is performed in a hydrogen or deuterium containing environment to load the polysilicon layer with fluorine (F) and hydrogen (H) atoms.

Abstract: Embodiments of the disclosure include an apparatus and method of forming an improved memory device. In some embodiments, the apparatus generally includes, for example, a plurality of alternating layers formed over a surface of a substrate including a plurality of word line layers with gate regions and a plurality of inter-word line dielectric layers; a channel; and an ONO layer stack disposed between the gate regions and the channel. The embodiments of the present disclosure may include at least one of: word line layers with gate regions that have sidewalls that have a reverse dome shape, sacrificial layers disposed between the word line layers and the inter-word line dielectric layers, or top and bottom dielectric layers deposited on top and bottom portions of the word line layers. Embodiments of the disclosure described herein may allow for the electric field of the gate regions of a memory device to be modified.

Abstract: A resistive random-access memory (ReRAM) device may include a thermally engineered layer that is positioned adjacent to an active layer and configured to act as a heat sink during filament formation in response to applied voltages. The thermally engineered layer may act as one of the electrodes on the ReRAM device and may be adjacent to any side of the active layer. The active layer may also include a plurality of individual active layers. Each of the active layers may be associated with a different dielectric constant, such that the middle active layer has a dielectric constant that is significantly higher than the other two surrounding active layers.

Abstract: Embodiments of the disclosure include an apparatus and method of forming a memory device with high-mobility oxide semiconductor channels. In some embodiments, the apparatus, for example, includes a plurality of alternating layers formed over a surface of a substrate; a gate coupled to each of the word line layers of the plurality of alternating layers; a multi-layer channel memory cell having a first end coupled to a source region, a second end coupled to a drain region, and extending in the first direction between the source region and the drain region, the multi-layer channel also having a first conductive layer and a second conductive layer, the first conductive layer being different from the second conductive layer; and an ONO layer stack disposed between the gates and the multi-layer channel, wherein the ONO layer stack extends in the first direction between the source region and the drain region.

Abstract: A ferroelectric tunnel junction (FTJ) memory device may include a first electrode and a ferroelectric layer comprising ferroelectric dipoles that may generate a first electric field. The first electric field may be oriented in a first direction when the device operates in an ON state. The device may also include a barrier layer that may generate a depolarizing second electric field that may be oriented in a second direction opposite of the first direction when the device operates in the ON state. The device may further include a second electrode. The first electrode and the second electrode may generate a third electric field that is oriented in the first direction when the device operates in the ON state.

Abstract: A method of characterizing defects in semiconductor layers may include forming a first electrode, a first barrier layer, a semiconductor layer, and a second electrode, where the first barrier layer is between the first electrode and the semiconductor layer, and the semiconductor layer is between the first barrier layer and the second electrode. The method may also include causing current to flow through the semiconductor layer, where the first barrier layer prevents the current from entering a conduction band of the semiconductor layer and instead causes current to flow through defects in the semiconductor layer. The method may also include characterizing the defects in the semiconductor layer based on the current flowing through the defects in the semiconductor layer.

Abstract: A selector device may include a first electrode, a tunneling layer, and a ferroelectric layer. The tunneling layer may be between the first electrode and the ferroelectric layer, and a thickness and dielectric constant of the tunneling layer relative to a thickness and dielectric constant of the ferroelectric layer may cause a depolarizing electric field induced in the first tunneling layer to be greater than or approximately equal to an electric field induced in an opposite direction by ferroelectric dipoles in the ferroelectric layer when a voltage is applied across the selector device. The device may also include a second electrode, and the ferroelectric layer may be between the tunneling layer and the second electrode. A second ing layer may also be added between the ferroelectric layer and the second electrode for bipolar selectors.

Abstract: A resistive random-access memory (ReRAM) device may include a thermally engineered layer that is positioned adjacent to an active layer and configured to act as a heat sink during filament formation in response to applied voltages. The thermally engineered layer may act as one of the electrodes on the ReRAM device and may be adjacent to any side of the active layer. The active layer may also include a plurality of individual active layers. Each of the active layers may be associated with a different dielectric constant, such that the middle active layer has a dielectric constant that is significantly higher than the other two surrounding active layers.

Abstract: A crested barrier device with interface switching modulation layers may include a first electrode, a first tunneling layer comprising a first dielectric constant, such as cobalt oxide, and one or more interface switching modulation (ISM) layers. Each of the one or more ISM layers may include a layer of hafnium oxide, a layer of silicon oxide comprising a second dielectric constant that is at least 1.5 times larger than the first dielectric constant, and a monolayer of titanium oxide between the layer of hafnium oxide and the layer of silicon oxide. The device may also include a second tunneling layer and a second electrode.

Abstract: An enhanced ferroelectric transistor may include Interface switching modulation (ISM) layers along with a ferroelectric layer in the gate of the transistor to increase a memory window while maintaining relatively low operating voltages. The enhanced ferroelectric transistor may be implemented as a memory device storing more than two bits of information in each memory cell. An enhanced ferroelectric tunnel junction device may include ISM layers and a ferroelectric layer to amplify the tunneling barriers in the device. The ISM layers may form material dipoles that add to the effect of ferroelectric dipoles in the ferroelectric material.

Abstract: A ferroelectric capacitor or a ferroelectric transistor may include a first metal layer having a first metal having a first work function, and a second metal layer having a second metal having a second work function. The capacitor may also include a a vertical electrode and a ferroelectric material that surrounds the vertical electrode and forms a plurality of switching regions in the ferroelectric material. The transistor may include a vertical channel, a vertical buffer layer that surround the vertical channel, and a ferroelectric material that surrounds the vertical buffer layer and forms a plurality of gate regions in the ferroelectric material.

Abstract: A device may include a first electrode, a barrier layer, and a tunneling layer having a first dielectric constant. The barrier layer may be between the first electrode and the tunneling layer. The device may also include an active layer having a second dielectric constant. The tunneling layer may be between the first electrode and the active layer. The device may further include a second electrode. The active layer may be between the tunneling layer and the second electrode.

Abstract: A selector device for a memory cell in a memory array may include a first electrode, and a separator that include a first region of a single-composition layer of a mixed ionic-electronic conduction material with a first concentration of defects; and a second region of a single-composition layer of a transitional metal oxide with a second concentration of defects that is different from the first concentration of defects. The selector device may also include a second electrode, where the separator is between the first electrode and the second electrode.

Abstract: One example provides a memory cell including a node, and a layer stack including a first electrode, a second electrode connected to the node, and a polarizable material layer disposed between the first and second electrodes and having at least two polarization states. A first transistor includes a source, a drain, and a gate terminal, with the gate terminal connected to the node. A selector element includes at least a first terminal and a second terminal, with the second terminal connected to the node.

Abstract: A crested barrier memory device may include a first electrode, a first self- rectifying layer, and a combined barrier and active layer. The first self-rectifying layer may be between the first electrode and the active layer. A conduction band offset between the first self-rectifying layer and the combined barrier and active layer may be greater than approximately 1.5 eV. A valence band offset between the first self-rectifying layer and the combined barrier and active layer may be less than approximately ?0.5 eV. The device may also include a second electrode. The active layer may be between the first self-rectifying layer and the second electrode.

Abstract: A resistive random-access memory (ReRAM) device may include a thermally engineered layer that is positioned adjacent to an active layer and configured to act as a heat sink during filament formation in response to applied voltages. The thermally engineered layer may act as one of the electrodes on the ReRAM device and may be adjacent to any side of the active layer. The active layer may also include a plurality of individual active layers. Each of the active layers may be associated with a different dielectric constant, such that the middle active layer has a dielectric constant that is significantly higher than the other two surrounding active layers.

Abstract: A semiconductor device that implements artificial neurons and synapses together on the semiconductor device includes a plurality of fins formed on the semiconductor device, and a plurality of gates formed around the plurality of fins to form a plurality of fin field-effect transistors (FinFETs). The plurality of FinFETs may form one or more artificial synapses and one or more artificial neurons. Each of the one or more artificial synapses may include two or more of the plurality of gates. Each of the one or more artificial neurons comprises one of the plurality of gates.

Abstract: One example provides a memory cell including a node, and a layer stack including a first electrode, a second electrode connected to the node, and a polarizable material layer disposed between the first and second electrodes and having at least two polarization states. A first transistor includes a source, a drain, and a gate terminal, with the gate terminal connected to the node. A selector element includes at least a first terminal and a second terminal, with the second terminal connected to the node.

Abstract: Integrated devices comprising pinched hysteresis loop (PHL) materials in a capacitor or a transistor stack are disclosed. PHL materials include field induced ferroelectrics (FFE), anti-ferroelectric (AFE) and relaxor type ferroelectric (RFE) materials. Each integrated device includes a material stack with a PHL material layer disposed between two electrodes. Application of this material is dependent on inducing of an electric field bias over the stack. According to one option, electrodes having different workfunction values can be employed to induce the required built-in bias field and enable use of PHL materials. According to another option, a PHL material and charges, e.g., a charge interlayer, are disposed between two electrodes such that an induced built-in bias field appears. Integrated devices employing the PHL material stack include memories, transistors, and piezo- and pyroelectric devices.