Abstract: An integrated circuit having a resistance-based or resistively switching memory cell, and a method for operating a resistively switching memory cell is disclosed. One embodiment is adapted to be put in a low-resistance state by applying a first threshold voltage and in a high-resistance state by applying a second threshold voltage, wherein reading out of the data content from the memory cell is performed by applying a voltage to the memory cell in the range of the first or second threshold voltage or a higher voltage.

Abstract: The present invention relates to a memory circuit and method of operating the same. In at least one embodiment, the memory circuit includes a resistive memory element coupled to a plate potential by a first terminal; a bit line which is connectable to a second terminal of the resistive memory element; a programming circuit operable to change the resistance of the resistive memory element; a bleeder circuit operable to provide a bleeding current to or from the bit line due to a change of the resistance of the resistive memory element caused by the programming circuit.

Abstract: A memory device and method of operating the same. In one embodiment, the memory device includes a resistive memory cell including a resistive memory element wherein the resistive memory element is designed to acquire a low resistance state when applying a programming voltage and acquire to a high resistance state when applying an erasing voltage; and wherein the writing time for changing the resistance state of the resistive memory element can be relatively reduced.

Abstract: An integrated circuit having a resistance-based or resistively switching memory cell, and a method for operating a resistively switching memory cell is disclosed. One embodiment is adapted to be put in a low-resistance state by applying a first threshold voltage and in a high-resistance state by applying a second threshold voltage, wherein reading out of the data content from the memory cell is performed by applying a voltage to the memory cell in the range of the first or second threshold voltage or a higher voltage.

Abstract: The invention relates to a method for reading a memory datum from a resistive memory cell comprising a selection transistor which is addressable via a control value, the method comprising detecting a cell current flowing through the resistive memory cell, setting the control value depending on the detected cell current, and providing an information associated to the control value as a memory datum.

Abstract: An integrated circuit having a resistive memory including a resistive memory element, a selection device, a conductive line, and a reference electrode is disclosed. In one embodiment, the conductive line is set to a first voltage for establishing a first resistive state of the resistive memory element and to a second voltage, being lower than the first voltage, for establishing a second resistive state of the resistive memory element. The reference electrode is coupled to the resistive memory element and is set to a voltage level being provided between the first voltage and the second voltage.

Abstract: A method and a circuit configuration for generating a reference voltage in a resistive semiconductor memory includes generating a reference voltage by connecting together two bitlines having different voltages. This method for generating a reference voltage can be used in a method and in a circuit configuration for reading at least one memory cell of a resistive memory cell array in a semiconductor memory. The generated reference voltage and a voltage dependent on the content of a resistive memory cell are applied to an amplifier to determine the content of the memory cell. The content of the memory cell is determined dependent on a relationship between the reference voltage and the voltage dependent on the content of the memory cell.

Abstract: A memory circuit comprises a plurality of parallel bit-lines connected to a plurality of memory cells, a plurality of sense amplifiers connected to the bit-lines and a plurality of switches each of which being connected to a respective pair of bit-lines out of the plurality of bit-lines for switchably short-circuiting the respective pair of bit-lines. The bit-lines of the respective pair of bit-lines are connected to two different sense amplifiers, and the bit-lines of the respective pair of bit-lines are adjacent to a further bit-line disposed between the bit-lines of the respective pair of bit-lines.

Abstract: A memory device comprises a memory cell array comprising a plurality of memory cells, bitlines being electrically connected to the memory cells of the memory cell array, amplifier circuits being electrically connected to the bitlines and amplifying electrical signals carried in the bitlines, the amplifier circuits being activated and deactivated by means of amplifier circuit control nodes, and at least one potential supplying unit, by means of which potentials can be supplied to the amplifier circuits such that, in the deactivated state of the amplifier circuits, a decrease or a prevention of leakage currents through the amplifier circuits is caused.

Abstract: The invention relates to a method for reading a memory datum from a resistive memory cell comprising a selection transistor which is addressable via a control value, the method comprising detecting a cell current flowing through the resistive memory cell, setting the control value depending on the detected cell current, and providing an information associated to the control value as a memory datum.

Abstract: A method and a circuit configuration for generating a reference voltage in a resistive semiconductor memory includes generating a reference voltage by connecting together two bitlines having different voltages. This method for generating a reference voltage can be used in a method and in a circuit configuration for reading at least one memory cell of a resistive memory cell array in a semiconductor memory. The generated reference voltage and a voltage dependent on the content of a resistive memory cell are applied to an amplifier to determine the content of the memory cell. The content of the memory cell is determined dependent on a relationship between the reference voltage and the voltage dependent on the content of the memory cell.

Abstract: The invention relates to a memory circuit comprising a resistive memory cell having a selection transistor and a resistive memory element connected in series, wherein the resistive memory element is coupled to a plate potential; and a control circuit to control the selection transistor by means of an activation signal a pre-charge circuit coupled with a node between the selection transistor and the resistive memory element and to apply a compensation potential to the node; wherein the control circuit controls the pre-charge circuit so that a compensation potential is applied to the node prior to a level transition of the activation signal.

Abstract: A memory device and method of operating the same. In one embodiment, the memory device includes a resistive memory cell including a resistive memory element wherein the resistive memory element is designed to acquire a low resistance state when applying a programming voltage and acquire to a high resistance state when applying an erasing voltage; and wherein the writing time for changing the resistance state of the resistive memory element can be relatively reduced.

Abstract: The present invention relates to a memory circuit and method of operating the same. In at least one embodiment, the memory circuit includes a resistive memory element coupled to a plate potential by a first terminal; a bit line which is connectable to a second terminal of the resistive memory element; a programming circuit operable to change the resistance of the resistive memory element; a bleeder circuit operable to provide a bleeding current to or from the bit line due to a change of the resistance of the resistive memory element caused by the programming circuit.