Abstract: A technique for easily and cost effectively installing solar photo-voltaic solar panels is provided. Solar panels are installed on pre-existing building structures to minimize the cost of installation. Pre-fabricated and field configurable components are used for mounting the solar panels such that the cost and ease of installation is made even more favorable to an average solar electricity consumer. An example of such a cost-effective implementation includes installing solar panels on pre-existing fences demarcating residences or commercial office spaces. L-shaped brackets are screwed on to the fence pillars. Pre-cut and adjustable aluminum or wooden rails are then mounted on the horizontal protruding arms of the L-shaped brackets. Solar photo-voltaic panels are later fitted on to the rails. Finally, quick disconnects are used to hook-up the solar panels to the DC-to-AC inverter in a desirable configuration to form the electrical circuit.

Abstract: A system for repairable interconnect links using laser energy in a semiconductor integrated circuit die. The integrated circuit die is fabricated to include a plurality of interconnect links. At least a first and a second interconnect element are included in the integrated circuit die. The first and second interconnect elements are couple via an interconnect link. An anti-reflective layer is disposed on a surface above the interconnect link. The anti-reflective layer is configured to increase an amount of laser energy absorbed by the interconnect link in order to fuse the interconnect link, and thereby repair the integrated circuit die.

Abstract: A patterned polishing pad adapted for use in a wafer polishing machine. The patterned polishing pad has a polishing surface adapted to contact frictionally a semiconductor wafer being polished in a chemical mechanical polishing machine. The polishing surface has a first region and a second region. The first region is adapted to contact frictionally the wafer and achieve a first process effect. The second region is adapted to contact frictionally the wafer and achieve a second process effect. The surface of the second region extends a predetermined protrusion amount above the polishing surface with respect to the surface of the first region.

Abstract: A semiconductor wafer polishing method comprises forming at least one alignment mark within an alignment area on a semiconductor wafer, forming a layer to be polished over the wafer, the layer being formed to be generally elevationally higher proximately about and surrounding the alignment area than within the alignment area, and polishing the layer. According to another aspect, a semiconductor wafer includes an alignment marking area formed relative to a surface of the wafer. At least one alignment mark is provided within the alignment area. A structure is formed about the alignment marking area and extends from the wafer surface a greater elevation than any elevation from such surface from which the alignment mark extends. Furthermore, a layer of material to be polished is provided over the structure to cause the material to be polished to be elevationally higher over the structure than over the alignment mark.

Abstract: A semiconductor wafer polishing method comprises forming at least one alignment mark within an alignment area on a semiconductor wafer, forming a layer to be polished over the wafer, the layer being formed to be generally elevationally higher proximately about and surrounding the alignment area than within the alignment area, and polishing the layer. According to another aspect, a semiconductor wafer includes an alignment marking area formed relative to a surface of the wafer. At least one alignment mark is provided within the alignment area. A structure is formed about the alignment marking area and extends from the wafer surface a greater elevation than any elevation from such surface from which the alignment mark extends. Furthermore, a layer of material to be polished is provided over the structure to cause the material to be polished to be elevationally higher over the structure than over the alignment mark.

Abstract: The present invention is an ultrasonic transducer slurry dispensing device and method for efficiently distributing slurry. The present invention utilizes ultrasonic energy to facilitate efficient slurry application in a IC wafer fabrication process to permits reduced manufacturing times and slurry consumption during IC wafer fabrication. In one embodiment a chemical mechanical polishing (CMP) ultrasonic transducer slurry dispenser device includes a slurry dispensing slot, a slurry chamber coupled and an ultrasonic transducer. The slurry chamber receives the slurry and transports it to the slurry dispensing slots that apply slurry to a polishing pad. The ultrasonic transducer transmits ultrasonic energy to the slurry.

Abstract: The present invention is a conditioning ring for conditioning a polishing pad in a chemical-mechanical polishing machine. The conditioning ring is comprised of a ring having a diameter and a conditioning surface substantially parallel to a plane defined by the diameter. The conditioning ring has an inner radius surface to the plane defined by the diameter, wherein the inner radius surface is adapted to accept a wafer. The conditioning ring has an outer radius surface opposite the inner radius surface and an upper surface opposite the conditioning surface. The chemical mechanical polishing machine polishes the wafer by moving the polishing pad with respect to the wafer while the wafer is in contact with the polishing pad. The conditioning surface is adapted to frictionally contact the polishing pad.

Abstract: A method of making an inter-metal oxide layer over a patterned metallization layer of a substrate, and the resulting structure having the inter-metal oxide layer are provided. The method includes depositing a fluorine doped high density plasma (HDP) oxide layer over the patterned metallization layer. The fluorine doped HDP oxide layer is configured to evenly deposit in high aspect ratio regions of the patterned metallization layer. The method also includes depositing a plasma enhanced chemical vapor deposition (PECVD) oxide layer over the fluorine doped HDP oxide layer. The PECVD oxide layer is doped with a phosphorous material. A CMP operation is then performed over the PECVD oxide layer to remove topographical oxide variations, such that the CMP operation will be configured to preferably leave at least a coating of the PECVD oxide layer over the HDP oxide layer.

Abstract: A method of isolating a semiconductor device by shallow trench isolation is provided by: (a) etching a trench into the surface of an integrated circuit; (b) depositing an oxide in the trench so that at least the upper portion of the oxide is silicon-rich; (c) providing a polysilicon gate electrode on the surface of the integrated circuit, with the gate electrode being provided substantially adjacent to the trench with a space between the trench and the gate electrode; (d) providing a spacer oxide to cover the trench oxide, the gate electrode and the space between the trench and the gate electrode, so that the spacer oxide has near-stoichiometric levels of silicon; and (e) etching the spacer oxide from the surface of the integrated circuit under conditions effective to selectively etch the spacer oxide from the upper surface of the integrated circuit and from the upper surface of the gate electrode without etching the trench oxide from the upper portion of the trench.

Abstract: A semiconductor wafer polishing method comprises forming at least one alignment mark within an alignment area on a semiconductor wafer, forming a layer to be polished over the wafer, the layer being formed to be generally elevationally higher proximately about and surrounding the alignment area than within the alignment area, and polishing the layer. According to another aspect, a semiconductor wafer includes an alignment marking area formed relative to a surface of the wafer. At least one alignment mark is provided within the alignment area. A structure is formed about the alignment marking area and extends from the wafer surface a greater elevation than any elevation from such surface from which the alignment mark extends. Furthermore, a layer of material to be polished is provided over the structure to cause the material to be polished to be elevationally higher over the structure than over the alignment mark.

Abstract: A technique for self-aligned silicidation of semiconductor devices is disclosed. This technique includes the formation of polysilicon device features extending from a semiconductor substrate. A coating is deposited on the features and substrate. Chemical mechanical polishing is performed to remove a portion of the coating to expose a polysilicon surface of the features. A metallic layer is formed to contact the exposed polysilicon surface of each of the features. A silicide layer is formed for each feature from the polysilicon and the metallic layer in contact therewith.

Abstract: The present invention comprises a chemical mechanical polishing (CMP) process for removing tungsten from the surface of a dielectric layer of a semiconductor wafer. The CMP process of the present invention removes tungsten from the surface of the dielectric layer while planarizing the dielectric surface. The system of the present invention places a wafer onto a pad of a CMP machine. The wafer includes an overlying layer of tungsten and an underlying layer of dielectric material. Slurry is dispensed onto the polishing pad and the wafer is polished by the CMP machine. The CMP machine polishes the wafer such that the CMP process has a substantially equal amount of tungsten to dielectric selectivity. This allows the CMP process to remove excess tungsten from the surface of the dielectric layer while simultaneously planarizing the dielectric layer. When the dielectric layer is sufficiently planarized and the excess tungsten has been removed, the wafer is removed from the CMP machine.