Patents by Inventor Miljan Vuletic

Miljan Vuletic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8923788
    Abstract: In one embodiment the present invention includes a method of generating an oscillating signal at different frequencies. The method comprises configuring a digitally controlled oscillator (DCO). The DCO is configured to generate the oscillating signal at a first frequency, and the DCO is configured to generate the oscillating signal at a second frequency. Additionally, the DCO is configured to transition from the first frequency to the second frequency during a transition time period. During the transition time period, the DCO activates the second frequency and deactivates the first frequency during a plurality of time intervals. The time intervals for activating the second frequency and deactivating the first frequency successively increase from the beginning of the transition time period to the end of the transition time period.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: December 30, 2014
    Assignee: Marvell International Ltd.
    Inventors: David Cousinard, Cao-Thong Tu, Miljan Vuletic, Lydi Smaini
  • Patent number: 8600324
    Abstract: In one embodiment the present invention includes a method of generating an oscillating signal at different frequencies. The method comprises configuring a digitally controlled oscillator (DCO). The DCO is configured to generate the oscillating signal at a first frequency, and the DCO is configured to generate the oscillating signal at a second frequency. Additionally, the DCO is configured to transition from the first frequency to the second frequency during a transition time period. During the transition time period, the DCO activates the second frequency and deactivates the first frequency during a plurality of time intervals. The time intervals for activating the second frequency and deactivating the first frequency successively increase from the beginning of the transition time period to the end of the transition time period.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: December 3, 2013
    Assignee: Marvell International Ltd
    Inventors: David Cousinard, Cao-Thong Tu, Miljan Vuletic, Lydi Smaini
  • Patent number: 8185696
    Abstract: Reconfigurable Systems-an-Chip (RSoCs) on the market consist of full-fledged processors and large Field-Programmable Gate Arrays (FPGAs). The latter can be used to implement the system glue logic, various peripherals, and application-specific coprocessors. Using FPGAs for application-specific coprocessors has certain speedup potentials, but it is less present in practice because of the complexity of interfacing the software application with the coprocessor. In the present application, we present a virtualisation layer consisting of an operating system extension and a hardware component. It lowers the complexity of interfacing and increases portability potentials, while it also allows the coprocessor to access the user virtual memory through a virtual memory window. The burden of moving data between processor and coprocessor is shifted from the programmer to the operating system.
    Type: Grant
    Filed: April 19, 2005
    Date of Patent: May 22, 2012
    Assignee: Ecole Polytechnique Federale de Lausanne (EPFL)
    Inventors: Miljan Vuletic, Laura Pozzi, Paolo Ienne
  • Patent number: 7741928
    Abstract: Circuits and methods for frequency modulation (FM) using a digital frequency-locked loop (DFLL). A digitally controlled oscillator (DCO) generates and adjusts a frequency of a modulated signal based on a digital tuning word. A DFLL control logic circuit receives a feedback of the modulated signal and generates a carrier signal word. A sigma delta modulator circuit receives an input signal and applies dithering to produce a dithered input signal word. An adder circuit receives and sums the dithered input signal word and the carrier signal word to produce the digital tuning word. The DFLL control logic circuit adjusts the carrier signal word to lock a carrier frequency of the modulated signal.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: June 22, 2010
    Assignee: Marvell International Ltd.
    Inventors: David Cousinard, Philippe Mosch, Lydi Smaini, Randy Tsang, Cao-Thong Tu, Miljan Vuletic
  • Publication number: 20100005272
    Abstract: Reconfigurable Systems-an-Chip (RSoCs) on the market consist of full-fledged processors and large Field-Programmable Gate Arrays (FPGAs). The latter can be used to implement the system glue logic, various peripherals, and application-specific coprocessors. Using FPGAs for application-specific coprocessors has certain speedup potentials, but it is less present in practice because of the complexity of interfacing the software application with the coprocessor. In the present application, we present a virtualisation layer consisting of an operating system extension and a hardware component. It lowers the complexity of interfacing and increases portability potentials, while it also allows the coprocessor to access the user virtual memory through a virtual memory window. The burden of moving data between processor and coprocessor is shifted from the programmer to the operating system.
    Type: Application
    Filed: April 19, 2005
    Publication date: January 7, 2010
    Inventors: Miljan Vuletic, Laura Pozzi, Paolo Ienne