Patents by Inventor Mill-Jer Wang
Mill-Jer Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240133942Abstract: A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.Type: ApplicationFiled: January 3, 2024Publication date: April 25, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao Chen, Mill-Jer Wang
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Publication number: 20240088124Abstract: A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.Type: ApplicationFiled: November 24, 2023Publication date: March 14, 2024Inventors: HSIANG-TAI LU, SHUO-MAO CHEN, MILL-JER WANG, FENG-CHENG HSU, CHAO-HSIANG YANG, SHIN-PUU JENG, CHENG-YI HONG, CHIH-HSIEN LIN, DAI-JANG CHEN, CHEN-HUA LIN
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Patent number: 11906573Abstract: A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.Type: GrantFiled: January 30, 2023Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao Chen, Mill-Jer Wang
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Publication number: 20240027514Abstract: A method includes: providing a first semiconductor device including a backside interconnection structure, the first semiconductor device being formed by a semiconductor process; and generating a physical failure analysis model by an inspection process. The inspection process includes: directing an electron beam toward the frontside of the first semiconductor device; and applying an electrical signal to an electrical contact of the first semiconductor device through an electrical path that goes through a shunt board attached to a switchable interface trace bank, the electrical contact being associated with a position of the electron beam. The method further includes: generating a parameter of a revised semiconductor process according to the physical failure analysis model and the semiconductor process; and forming a second semiconductor device by the revised semiconductor process using the parameter.Type: ApplicationFiled: February 13, 2023Publication date: January 25, 2024Inventors: Chia-Hong Lin, Yu-Ting Lin, Mill-Jer Wang
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Patent number: 11855066Abstract: A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.Type: GrantFiled: May 13, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsiang-Tai Lu, Shuo-Mao Chen, Mill-Jer Wang, Feng-Cheng Hsu, Chao-Hsiang Yang, Shin-Puu Jeng, Cheng-Yi Hong, Chih-Hsien Lin, Dai-Jang Chen, Chen-Hua Lin
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Patent number: 11852672Abstract: A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.Type: GrantFiled: July 27, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTORMANUFACTURING COMPANY LIMITEDInventors: Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Chuan-Ching Wang, Hao Chen
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Publication number: 20230333150Abstract: A testing device for testing an antenna is provided. The testing device includes a housing, an antenna module for holding the antenna and disposed under the housing, and a receiving module disposed on the housing. The antenna module includes a base and a flexible film disposed on the base. The receiving module includes a substrate, a coupling radiation element disposed on the substrate and a support disposed on the substrate and having an opening. The antenna is partially exposed from the opening.Type: ApplicationFiled: June 22, 2023Publication date: October 19, 2023Inventors: Chi-Chang LAI, Kai-Yi TANG, Mill-Jer WANG
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Patent number: 11726112Abstract: A circuit probe includes a shielding probe having a base and a conductive probe ring on the base. A shielding cage is attached to the conductive probe ring and has an interior. The shielding cage is configured to be positioned to contain in the interior of the shielding cage at least one integrated circuit formed on a wafer, and to provide electromagnetic shielding of the at least one integrated circuit during testing of the at least one integrated circuit.Type: GrantFiled: September 16, 2019Date of Patent: August 15, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ching-Nen Peng, Hsien-Tang Wang, Mill-Jer Wang, Chi-Chang Lai
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Patent number: 11726122Abstract: A testing device for testing an antenna is provided. The testing device includes a housing, an antenna module, and a receiving module. The antenna module is used for holding the antenna and disposed on the housing, wherein the antenna is coupled to an antenna testing apparatus. The receiving module is disposed on the housing and includes a coupling radiation element physically separated from the antenna, wherein the receiving module is configured to receive an excited signal emitted from the antenna.Type: GrantFiled: June 29, 2020Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Chang Lai, Kai-Yi Tang, Mill-Jer Wang
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Publication number: 20230253273Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and multiple first conductive lines over the semiconductor substrate. The first conductive lines are not electrically connected to each other. The semiconductor device structure also includes multiple first magnetic structures wrapped around portions of the first conductive lines and multiple second conductive lines over the semiconductor substrate. The second conductive lines are electrically connected in series. The semiconductor device structure further includes multiple second magnetic structures wrapped around portions of the second conductive lines. A size of each of the second magnetic structures and a size of each of the first magnetic structures are substantially the same.Type: ApplicationFiled: April 14, 2023Publication date: August 10, 2023Inventors: Mill-Jer WANG, Tang-Jung CHIU, Chi-Chang LAI, Chia-Heng TSAI, Mirng-Ji LII, Weii LIAO
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Patent number: 11693045Abstract: A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.Type: GrantFiled: August 9, 2022Date of Patent: July 4, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao Chen, Mill-Jer Wang
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Publication number: 20230168296Abstract: A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.Type: ApplicationFiled: January 30, 2023Publication date: June 1, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao Chen, Mill-Jer Wang
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Patent number: 11631621Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first magnetic element and a second magnetic element over the semiconductor substrate. The semiconductor device structure also includes a first conductive line extending exceeding an edge of the first magnetic element. The semiconductor device structure further includes a second conductive line extending exceeding an edge of the second magnetic element. The second conductive line is electrically connected to the first conductive line.Type: GrantFiled: May 24, 2021Date of Patent: April 18, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Mill-Jer Wang, Tang-Jung Chiu, Chi-Chang Lai, Chia-Heng Tsai, Mirng-Ji Lii, Weii Liao
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Publication number: 20230065443Abstract: A probe head structure is provided. The probe head structure includes a flexible substrate having a top surface and a bottom surface. The probe head structure includes a first probe pillar passing through the flexible substrate. The first probe pillar has a first protruding portion protruding from the bottom surface. The probe head structure includes a redistribution structure on the top surface of the flexible substrate and the first probe pillar. The redistribution structure is in direct contact with the flexible substrate and the first probe pillar. The redistribution structure includes a dielectric structure and a wiring structure in the dielectric structure. The wiring structure is electrically connected to the first probe pillar. The probe head structure includes a wiring substrate over the redistribution structure. The probe head structure includes a first conductive bump connected between the wiring substrate and the redistribution structure.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Wen-Yi LIN, Hao CHEN, Chuan-Hsiang SUN, Mill-Jer WANG, Chien-Chen LI, Chen-Shien CHEN
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Patent number: 11585831Abstract: A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps.Type: GrantFiled: August 18, 2020Date of Patent: February 21, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Mill-Jer Wang, Ching-Fang Chen, Sandeep Kumar Goel, Chung-Sheng Yuan, Chao-Yang Yeh, Chin-Chou Liu, Yun-Han Lee, Hung-Chih Lin
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Patent number: 11585846Abstract: A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.Type: GrantFiled: March 2, 2020Date of Patent: February 21, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao Chen, Mill-Jer Wang
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Patent number: 11579190Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.Type: GrantFiled: May 23, 2022Date of Patent: February 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Mill-Jer Wang, Kuo-Chuan Liu, Ching-Nen Peng, Hung-Chih Lin, Hao Chen
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Publication number: 20220381817Abstract: A testing module for a semiconductor wafer-form package includes a circuit board structure, first connectors, a first connecting structure, second connectors, third connectors and a first bridge connector. The circuit board structure includes two edge regions and a main region located therebetween. The first connectors are located over the edge regions and connected to the circuit board structure. The first connecting structure is located over and distant from the circuit board structure. The second connectors and third connectors are located over and connected to the first connecting structure, where the third connectors are configured to transmit electric signals for testing the semiconductor wafer-form package being placed over the main region. The first bridge connector is electrically coupling the circuit board structure and the first connecting structure by connecting the second connectors and the first connectors.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao Chen, Mill-Jer Wang
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Publication number: 20220357389Abstract: A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.Type: ApplicationFiled: July 27, 2022Publication date: November 10, 2022Inventors: Mill-Jer WANG, Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Chuan-Ching Wang, Hao Chen
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Patent number: 11467203Abstract: A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.Type: GrantFiled: July 27, 2020Date of Patent: October 11, 2022Inventors: Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Chuan-Ching Wang, Hao Chen