Abstract: Computerized payment method using short, temporary, transaction ID (TID) symbols. Payees (merchants) register their unique ID telecommunications devices (e.g. Smartphone and phone number), and financial institution with a payment server. When a payee initiates a financial transaction by requesting a TID from the server for that amount. The server sends a TID to the payee, which the payee then communicates to the payer (customer). The payer turn relays this TID to the server, which validates the transaction using the payer device. The server then releases funds to the payee. The server can preserve audit records, but security is enhanced because the merchant never directly accesses the customer's financial account. GPS coordinates and/or payer provided Group IDs may also be used to reduce the number of symbols used in the TID. For use case convenience, phone numbers may be used as a type of globally unique Group identification (GroupID).

Abstract: Provided is an end-to-end flow control management for a system on chip interface. As tokens are injected into agents arranged in a computer network the input point for the token is dynamically changed such that tokens are not always injected into the same agent. Additionally or alternatively, as tokens are injected into a token ring, the tokens are initially not activated until a predetermined event occurs (e.g., after a specific number of hops). Additionally or alternatively, also provided is a free pool manager that can keep at least some high priority slots available by consuming lower priority slots first.

Abstract: A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

Abstract: Proving for a framework for propagating priorities to a memory subsystem in a computing system environment is disclosed herein. By way of example, a memory access handler is provided for managing memory access requests and determining associated priorities. The memory access handler includes logic configured for propagating memory requests and the associated priorities to lower levels of a computer hierarchy. A memory subsystem receives the memory access requests and the priorities.

Abstract: An adapter or bridging device that provides both a wired audio or audio and video female jack connectors for wired devices such as wired earphones, headphones and wired video headsets; as well as a wireless link to nearby handheld computerized devices such as mobile phones (e.g. smartphones). The device may be configured to be clipped to the user's clothing, as well as to interface with pairing control devices to easily form Bluetooth, WiFi, or other type wireless links. The device may also include at least one computer processor to manage the wireless link, control the attached wired headphones or video headsets, as well as perform compression and decompression functions as desired.

Abstract: Proving for a framework for propagating priorities to a memory subsystem in a computing system environment is disclosed herein. By way of example, a memory access handler is provided for managing memory access requests and determining associated priorities. The memory access handler includes logic configured for propagating memory requests and the associated priorities to lower levels of a computer hierarchy. A memory subsystem receives the memory access requests and the priorities.

Abstract: An adapter or bridging device that provides both a wired audio or audio and video female jack connectors for wired devices such as wired earphones, headphones and wired video headsets; as well as a wireless link to nearby handheld computerized devices such as mobile phones (e.g. smartphones). The device may be configured to be clipped to the user's clothing, as well as to interface with pairing control devices to easily form Bluetooth, WiFi, or other type wireless links. The device may also include at least one computer processor to manage the wireless link, control the attached wired headphones or video headsets, as well as perform compression and decompression functions as desired.

Abstract: A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

Abstract: Proving for a framework for propagating priorities to a memory subsystem in a computing system environment is disclosed herein. By way of example, a memory access handler is provided for managing memory access requests and determining associated priorities. The memory access handler includes logic configured for propagating memory requests and the associated priorities to lower levels of a computer hierarchy. A memory subsystem receives the memory access requests and the priorities.

Abstract: An adapter or bridging device that provides both a wired audio or audio and video female jack connectors for wired devices such as wired earphones, headphones and wired video headsets; as well as a wireless link to nearby handheld computerized devices such as mobile phones (e.g. smartphones). The device may be configured to be clipped to the user's clothing, as well as to interface with pairing control devices to easily form Bluetooth, WiFi, or other type wireless links. The device may also include at least one computer processor to manage the wireless link, control the attached wired headphones or video headsets, as well as perform compression and decompression functions as desired.

Abstract: A computerized method of terminating audio telephone calls that provides the other party with more information as to why the telephone call was terminated. This method, which is particularly useful for computerized smartphones equipped with voice and data channel communications methods, automatically provides the user with a variety of different informative text messages that can be selected by the user and sent to the other party at the time that a voice call is terminated.

Abstract: Systems and methods that facilitate reduced latency via stashing in multi-level cache memory architectures of systems on chips (SoCs) are provided. One method involves stashing, by a device includes a plurality of multi-processor central processing unit cores, first data into a first cache memory of a plurality of cache memories, the plurality of cache memories being associated with a multi-level cache memory architecture. The method also includes generating control information including: a first instruction to cause monitoring contents of a second cache memory of the plurality of cache memories to determine whether a defined condition is satisfied for the second cache memory; and a second instruction to cause prefetching the first data into the second cache memory of the plurality of cache memories based on a determination that the defined condition is satisfied.

Abstract: Method of using a computerized smartphone to navigate remote auto attendant telephony systems with a menu structure. The auto attendant's menu structure is put into an online computer database. The caller uses the smartphone to call and establish a voice channel with remote auto attendant telephony system (using the telephone number of that system), software applications running on the caller's smartphone communication device intercept the telephone number and along with the voice channel, also establish a data channel with the online computer accessible database. The caller's smartphone retrieves at least some of the menu structure of the auto attendant telephony system through this data channel, and displays at least some of the menu structure of the remote auto attendant telephony system on the graphical user interface of the user's smartphone synchronized, with the audio delivery of the menu structure, thus facilitating interactions with the auto attendant system.

Abstract: A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

Abstract: A processor includes a plurality of general purpose registers and cryptographic logic to encrypt and decrypt information. The cryptographic logic is to support a Data Encryption Standard (DES) algorithm, a triple DES (3DES) algorithm, a Rivest-Shamir-Adleman (RSA) algorithm, and a Diffie Hellman algorithm. The processor also includes a plurality of memory partition registers to define a physical address range in a dynamic random access memory for use as a secure memory partition. The processor also includes a plurality of execution units coupled to the plurality of general purpose registers, the plurality of memory partition registers, and the cryptographic logic. The processor also includes secure partition enforcement logic coupled to the plurality of execution units and the memory partition registers, the secure partition enforcement logic to selectively permit read or write access to the dynamic random access memory.

Abstract: Systems and methods that facilitate reduced latency via stashing in multi-level cache memory architectures of systems on chips (SoCs) are provided. One method involves stashing, by a device includes a plurality of multi-processor central processing unit cores, first data into a first cache memory of a plurality of cache memories, the plurality of cache memories being associated with a multi-level cache memory architecture. The method also includes generating control information including: a first instruction to cause monitoring contents of a second cache memory of the plurality of cache memories to determine whether a defined condition is satisfied for the second cache memory; and a second instruction to cause prefetching the first data into the second cache memory of the plurality of cache memories based on a determination that the defined condition is satisfied.

Abstract: A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

Abstract: A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

Abstract: A processor includes a first register with first, second, third, and fourth data elements. A second register to hold fifth, sixth, seventh, and eighth data elements, and a third register. A decoder to decode a packed instruction to identify the first and second registers as source registers and the third register as a destination register. And to decode a pack instruction to identify a fourth and a fifth register each having 16-bit data elements. At least one functional unit, responsive to the packed instruction, to store a result in the third register including only half of all data elements of each of the first and second registers, including only corresponding data elements from corresponding positions in the first and second registers, and responsive to the pack instruction to store a result that is to include an 8-bit data element for each 16-bit data element in the fourth and fifth registers.