Abstract: An electronic circuit comprising an SRAM memory, a control unit, an error detection and correction module and a scrubbing module. The electronic circuit further comprises an integrated SEU monitor of the SRAM memory. The SEU monitor does not use standalone or specialized SRAM memories or particle detectors. Rather, the same SRAM memory that is used for the main operation as a storage element of the electronic circuit serves simultaneously as detector for the SEU monitor. The proposed SEU monitor enables real-time monitoring of the SEU rate in order to detect early the high radiation levels and apply appropriate hardening measures. Furthermore, a method for monitoring an SEU rate and determining permanent faults in an electronic circuit is suggested.

Abstract: The invention is directed to a self-correcting modular-redundancy-memory device, comprising three bistable-memory elements and a majority voter. The bistable-memory elements receive respective binary data signal, clock signal, and a feedback signal. Each of the bistable-memory elements is configured, in response to the clock signal assuming a first value, to provide a binary output signal with an output-signal value correlated to a data-signal value of the data signal, and in response to the clock signal assuming a second clock-signal value, to provide the output signal with the output-signal value indicative of a current feedback-signal value of the feedback signal. The majority voter receives the output signals each of the bistable-memory elements and is configured to provide the feedback signal with the feedback-signal value indicative of that output-signal value taken on by a majority of the currently received output signals.

Abstract: The invention is directed to a self-correcting modular-redundancy-memory device, comprising three bistable-memory elements and a majority voter. The bistable-memory elements receive respective binary data signal, clock signal, and a feedback signal. Each of the bistable-memory elements is configured, in response to the clock signal assuming a first value, to provide a binary output signal with an output-signal value correlated to a data-signal value of the data signal, and in response to the clock signal assuming a second clock-signal value, to provide the output signal with the output-signal value indicative of a current feedback-signal value of the feedback signal. The majority voter receives the output signals each of the bistable-memory elements and is configured to provide the feedback signal with the feedback-signal value indicative of that output-signal value taken on by a majority of the currently received output signals.

Abstract: An electronic circuit comprising an SRAM memory, a control unit, an error detection and correction module and a scrubbing module. The electronic circuit further comprises an integrated SEU monitor of the SRAM memory. The SEU monitor does not use standalone or specialized SRAM memories or particle detectors. Rather, the same SRAM memory that is used for the main operation as a storage element of the electronic circuit serves simultaneously as detector for the SEU monitor. The proposed SEU monitor enables real-time monitoring of the SEU rate in order to detect early the high radiation levels and apply appropriate hardening measures. Furthermore, a method for monitoring an SEU rate and determining permanent faults in an electronic circuit is suggested.

Abstract: The IEEE 802.11a standard uses OFDM, where the transmission is divided into several orthogonal sub-carriers. Here, an algorithm is used for the frame detection; a simplified differentiator obtains an absolute maximum in the differentiated signal at that point where the first plateau in JF(k) starts; a peak detector obtains the position of the absolute maximum in the differentiated signal, divides the problem into relative peak detection and falling edge detection; a simplified XNOR-based crosscorrelator is used, where the simplifications are based on the knowledge of the reference; a particular solution is provided for the CORDIC algorithm in the vectoring mode for arctangent calculation; hardware structuring is presented for the whole synchronizer so as to obtain a simple control mechanism and the separation of this structure into different clock domains, each one being activated only to perform its operation and deactivated afterwards.

Abstract: A method of reducing a phase error caused by a plurality of error sources in a signal in the form of a sequence of a plurality of digital partial signals associated with a number of subcarriers (k) of a carrier, the method including, for each partial signal: equalization of the partial signal (Y(i,k)), estimation of the phase error of the equalized partial signal (X(i,k)), and correction of the estimated phase error of the equalized partial signal. One embodiment provides the equalization with elimination of an accumulation of a phase error over the sequence of the partial signals. In addition the estimation includes detecting a plurality of predetermined pilot signals and determining a phase correction factor on the basis of the detected pilot signals, with at least one multiplication operation carried out solely by means of shift and adding operations. A corresponding apparatus is also described.

Abstract: The invention concerns an asynchronous wrapper for a globally asynchronous, locally synchronous circuit. The asynchronous wrapper operates with a request signal-driven clock control, supplemented by a local clock unit in the absence of request signals. It has at least one input unit which is adapted to receive a request signal from outside and to indicate to the outside the reception of the request signal by the delivery of an associated acknowledgement signal, and a pausable clock unit which is adapted to repeatedly produce a first clock signal and to deliver it to an internally synchronous circuit block associated with the asynchronous wrapper. The input unit is adapted to produce, if a request signal is applied, a second clock signal which is in a defined time relationship with the request signal and to deliver it to the internally synchronous circuit block.

Abstract: A method of reducing a phase error caused by a plurality of error sources in a signal which is present in a digital frequency representation in the form of a sequence of a plurality of digital partial signals which are associated with a number of subcarriers (k) of a carrier. The following steps are performed for each partial signal: equalization of the partial signal (Y(i,k)), estimation of the phase error of the equalized partial signal (X(i,k)), and correction of the estimated phase error of the equalized partial signal. An embodiment of that method provides that the equalization step includes the elimination of an accumulation of a phase error of the partial signal, caused by a sampling frequency error, over the sequence of the partial signals, such that the accumulation is negligible.

Abstract: The invention concerns an asynchronous wrapper for a globally asynchronous, locally synchronous circuit. The asynchronous wrapper operates with a request signal-driven clock control, supplemented by a local clock unit in the absence of request signals. It has at least one input unit which is adapted to receive a request signal from outside and to indicate to the outside the reception of the request signal by the delivery of an associated acknowledgement signal, and a pausable clock unit which is adapted to repeatedly produce a first clock signal and to deliver it to an internally synchronous circuit block associated with the asynchronous wrapper. The input unit is adapted to produce, if a request signal is applied, a second clock signal which is in a defined time relationship with the request signal and to deliver it to the internally synchronous circuit block.

Abstract: The IEEE 802.11a standard uses OFDM, where the transmission is divided into several orthogonal sub-carriers. Here, an algorithm is used for the frame detection; a simplified differentiator obtains an absolute maximum in the differentiated signal at that point where the first plateau in JF(k) starts; a peak detector obtains the position of the absolute maximum in the differentiated signal, divides the problem into relative peak detection and falling edge detection; a simplified XNOR-based crosscorrelator is used, where the simplifications are based on the knowledge of the reference; a particular solution is provided for the CORDIC algorithm in the vectoring mode for arctangent calculation; hardware structuring is presented for the whole synchronizer so as to obtain a simple control mechanism and the separation of this structure into different clock domains, each one being activated only to perform its operation and deactivated afterwards.