Patents by Inventor Milos Trajkovic
Milos Trajkovic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240111525Abstract: Methods and systems relating to computational hardware are disclosed herein. One disclosed method for executing a multiplication computation using a computational hardware block includes storing a first operand and a second operand for the multiplication computation. The first operand includes a first set of bit strings. The second operand includes a second set of bit strings. The method also includes multiplying the first set of bit strings and the second set of bit strings in a set of temporal phases using the computational hardware block. Each temporal phase uses a different group of bit strings from the first set of bit strings and the second set of bit strings. A cardinality of the set of temporal phases is determined by a fidelity control value. The fidelity control value adaptively sets a fidelity of execution of the multiplication computation.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Inventors: Ljubisa Bajic, Milos Trajkovic, Syed Gilani
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Publication number: 20230153110Abstract: Methods and systems relating to improved processing architectures with pre-staged instructions are disclosed herein. A disclosed processor includes a memory, at least one functional processing unit, a bus, a set of instruction registers configured to be loaded, using the bus, with a set of pre-staged instructions from the memory, and a logic circuit configured to provide the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit in response to receiving an instruction from the instruction memory.Type: ApplicationFiled: January 17, 2023Publication date: May 18, 2023Applicant: Tenstorrent Inc.Inventors: Miles Robert Dooley, Milos Trajkovic, Rakesh Shaji Lal, Stanislav Sokorac
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Patent number: 11599358Abstract: Methods and systems relating to improved processing architectures with pre-staged instructions are disclosed herein. A disclosed processor includes an instruction memory, at least one functional processing unit, a bus, a set of instruction registers configured to be loaded, using the bus, with a set of pre-staged instructions from the instruction memory, and a logic circuit configured to provide the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit in response to receiving an instruction from the instruction memory.Type: GrantFiled: August 12, 2021Date of Patent: March 7, 2023Assignee: Tenstorrent Inc.Inventors: Miles Robert Dooley, Milos Trajkovic, Rakesh Shaji Lal, Stanislav Sokorac
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Publication number: 20230051122Abstract: Methods and systems relating to improved processing architectures with pre-staged instructions are disclosed herein. A disclosed processor includes an instruction memory, at least one functional processing unit, a bus, a set of instruction registers configured to be loaded, using the bus, with a set of pre-staged instructions from the instruction memory, and a logic circuit configured to provide the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit in response to receiving an instruction from the instruction memory.Type: ApplicationFiled: August 12, 2021Publication date: February 16, 2023Applicant: Tenstorrent Inc.Inventors: Miles Robert Dooley, Milos Trajkovic, Rakesh Shaji Lal, Stanislav Sokorac
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Publication number: 20230041130Abstract: Methods and systems related to the efficient execution of complex computations by a multicore processor and the movement of data among the various processing cores in the multicore processor are disclosed. A multicore processor includes a set of processing cores and associated sets of processing pipelines, core controllers, routers, and network interface units. The multicore processor also includes a computation layer, for conducting computations using the set of processing cores, with executable instructions for the set of processing pipelines which are executed by the set of core controllers. The multicore processor also includes a network-on-chip layer, for connecting the set of processing cores in the multicore processor, with executable instructions for the set of routers and the set of network interface units.Type: ApplicationFiled: September 14, 2022Publication date: February 9, 2023Inventors: Davor Capalija, Ivan Matosevic, Jasmina Vasiljevic, Utku Aydonat, Andrew Lewycky, S. Alexander Chin, Ljubisa Bajic, Alex Cejkov, Milos Trajkovic
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Patent number: 11567764Abstract: Methods and systems relating to improved processing architectures with pre-staged instructions are disclosed herein. A disclosed processor includes an instruction memory, at least one functional processing unit, a bus, a set of instruction registers configured to be loaded, using the bus, with a set of pre-staged instructions from the instruction memory, and a logic circuit configured to provide the set of pre-staged instructions from the set of instruction registers to the at least one functional processing unit in response to receiving an instruction from the instruction memory.Type: GrantFiled: August 12, 2021Date of Patent: January 31, 2023Assignee: Tenstorrent Inc.Inventors: Miles Robert Dooley, Milos Trajkovic, Rakesh Shaji Lal, Stanislav Sokorac
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Publication number: 20220222086Abstract: Processing cores with the ability to suppress operations based on a contribution estimate for those operations for purposes of increasing the overall performance of the core are disclosed. Associated methods that can be conducted by such processing cores are also disclosed. One such method includes generating a reference value for a composite computation. A complete execution of the composite computation generates a precise output and requires execution of a set of component computations. The method also includes generating a component computation approximation. The method also includes evaluating the component computation approximation with the reference value. The method also includes executing a partial execution of the composite computation using the component computation approximation to produce an estimated output.Type: ApplicationFiled: March 28, 2022Publication date: July 14, 2022Applicant: Tenstorrent Inc.Inventors: Ljubisa Bajic, Milos Trajkovic, Ivan Hamer, Syed Gilani
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Patent number: 11301264Abstract: Processing cores with the ability to suppress operations based on a contribution estimate for those operations for purposes of increasing the overall performance of the core are disclosed. Associated methods that can be conducted by such processing cores are also disclosed. One such method includes generating a reference value for a composite computation. A complete execution of the composite computation generates a precise output and requires execution of a set of component computations. The method also includes generating a component computation approximation. The method also includes evaluating the component computation approximation with the reference value. The method also includes executing a partial execution of the composite computation using the component computation approximation to produce an estimated output.Type: GrantFiled: February 11, 2020Date of Patent: April 12, 2022Assignee: Tenstorrent Inc.Inventors: Ljubisa Bajic, Milos Trajkovic, Ivan Hamer, Syed Gilani
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Publication number: 20210382716Abstract: A processing core and associated methods for the efficient execution of a directed graph are disclosed. A disclosed processing core includes a memory and a first data tile stored in the memory. The first data tile includes a first set of data elements and metadata stored in association with the first set of data elements. The processing core also includes a second data tile stored in the memory. The second data tile includes a second set of data elements. The processing core also includes an arithmetic logic unit configured to conduct an arithmetic logic operation using data from the first set of data elements and the second set of data elements. The processing core also includes a control unit configured to evaluate the metadata and control the arithmetic logic unit to conditionally execute the arithmetic logic operation based on the evaluation of the metadata.Type: ApplicationFiled: August 23, 2021Publication date: December 9, 2021Applicant: Tenstorrent Inc.Inventors: Ljubisa Bajic, Milos Trajkovic, Ivan Hamer, Lejla Bajic, Aleksandar Cejkov
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Patent number: 11113051Abstract: A processing core and associated methods for the efficient execution of a directed graph are disclosed. A disclosed processing core comprises a memory and a first data tile stored in the memory. The first data tile includes a first set of data elements and metadata stored in association with the first set of data elements. The processing core also comprises a second data tile stored in the memory. The second data tile includes a second set of data elements. The processing core also comprises an arithmetic logic unit configured to conduct an arithmetic logic operation using data from the first set of data elements and the second set of data elements. The processing core also comprises a control unit configured to evaluate the metadata and control the arithmetic logic unit to conditionally execute the arithmetic logic operation based on the evaluation of the metadata.Type: GrantFiled: October 8, 2018Date of Patent: September 7, 2021Assignee: Tenstorrent Inc.Inventors: Ljubisa Bajic, Milos Trajkovic, Ivan Hamer, Lejla Bajic, Aleksandar Cejkov
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Publication number: 20210042118Abstract: A processing core for the efficient execution of a directed graph is disclosed. The processing core includes a memory and a first and a second data tile stored in the memory. The first and second data tiles include a first and a second set of data elements stored contiguously in the memory. The processing core also includes metadata relationally stored with the first data tile in the memory. The processing core also includes an execution engine, a control unit, and an instruction. Execution of the instruction uses the execution engine, a first data element in the first set of data elements, and a second data element in the second set of data elements. The control unit conditions execution of the instruction using the metadata. A standard execution of the instruction generates a standard output. A conditional execution of the instruction operation generates a conditionally executed output.Type: ApplicationFiled: October 26, 2020Publication date: February 11, 2021Applicant: Tenstorrent Inc.Inventors: Ljubisa Bajic, Milos Trajkovic, Ivan Hamer
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Patent number: 10817293Abstract: A processing core for the efficient execution of a directed graph is disclosed. The processing core includes a memory and a first and a second data tile stored in the memory. The first and second data tiles include a first and a second set of data elements stored contiguously in the memory. The processing core also includes metadata relationally stored with the first data tile in the memory. The processing core also includes an execution engine, a control unit, and an instruction. Execution of the instruction uses the execution engine, a first data element in the first set of data elements, and a second data element in the second set of data elements. The control unit conditions execution of the instruction using the metadata. A standard execution of the instruction generates a standard output. A conditional execution of the instruction operation generates a conditionally executed output.Type: GrantFiled: April 26, 2018Date of Patent: October 27, 2020Assignee: Tenstorrent Inc.Inventors: Ljubisa Bajic, Milos Trajkovic, Ivan Hamer
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Publication number: 20200174799Abstract: Processing cores with the ability to suppress operations based on a contribution estimate for those operation for purposes of increasing the overall performance of the core are disclosed. Associated methods that can be conducted by such processing cores are also disclosed. One such method includes generating a reference value for a composite computation. A complete execution of the composite computation generates a precise output and requires execution of a set of component computations. The method also includes generating a component computation approximation. The method also includes evaluating the component computation approximation with the reference value. The method also includes executing a partial execution of the composite computation using the component computation approximation to produce an estimated output.Type: ApplicationFiled: February 11, 2020Publication date: June 4, 2020Applicant: Tenstorrent Inc.Inventors: Ljubisa Bajic, Milos Trajkovic, Ivan Hamer, Syed Gilani
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Patent number: 10585679Abstract: Processing cores with the ability to suppress operations based on a contribution estimate for those operation for purposes of increasing the overall performance of the core are disclosed. Associated methods that can be conducted by such processing cores are also disclosed. One such method includes generating a reference value for a composite computation. A complete execution of the composite computation generates a precise output and requires execution of a set of component computations. The method also includes generating a component computation approximation. The method also includes evaluating the component computation approximation with the reference value. The method also includes executing a partial execution of the composite computation using the component computation approximation to produce an estimated output.Type: GrantFiled: May 20, 2019Date of Patent: March 10, 2020Assignee: Tenstorrent Inc.Inventors: Ljubisa Bajic, Milos Trajkovic, Ivan Hamer, Syed Gilani
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Publication number: 20190272183Abstract: Processing cores with the ability to suppress operations based on a contribution estimate for those operation for purposes of increasing the overall performance of the core are disclosed. Associated methods that can be conducted by such processing cores are also disclosed. One such method includes generating a reference value for a composite computation. A complete execution of the composite computation generates a precise output and requires execution of a set of component computations. The method also includes generating a component computation approximation. The method also includes evaluating the component computation approximation with the reference value. The method also includes executing a partial execution of the composite computation using the component computation approximation to produce an estimated output.Type: ApplicationFiled: May 20, 2019Publication date: September 5, 2019Applicant: Tenstorrent Inc.Inventors: Ljubisa Bajic, Milos Trajkovic, Ivan Hamer, Syed Gilani
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Patent number: 10318317Abstract: Processing cores with the ability to suppress operations based on a contribution estimate for those operation for purposes of increasing the overall performance of the core are disclosed. Associated methods that can be conducted by such processing cores are also disclosed. One such method includes generating a reference value for a composite computation. A complete execution of the composite computation generates a precise output and requires execution of a set of component computations. The method also includes generating a component computation approximation. The method also includes evaluating the component computation approximation with the reference value. The method also includes executing a partial execution of the composite computation using the component computation approximation to produce an estimated output.Type: GrantFiled: May 10, 2018Date of Patent: June 11, 2019Assignee: Tenstorrent Inc.Inventors: Ljubisa Bajic, Milos Trajkovic, Ivan Hamer, Syed Gilani
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Publication number: 20190050224Abstract: A processing core and associated methods for the efficient execution of a directed graph are disclosed. A disclosed processing core comprises a memory and a first data tile stored in the memory. The first data tile includes a first set of data elements and metadata stored in association with the first set of data elements. The processing core also comprises a second data tile stored in the memory. The second data tile includes a second set of data elements. The processing core also comprises an arithmetic logic unit configured to conduct an arithmetic logic operation using data from the first set of data elements and the second set of data elements. The processing core also comprises a control unit configured to evaluate the metadata and control the arithmetic logic unit to conditionally execute the arithmetic logic operation based on the evaluation of the metadata.Type: ApplicationFiled: October 8, 2018Publication date: February 14, 2019Applicant: Tenstorrent Inc.Inventors: Ljubisa Bajic, Milos Trajkovic, Ivan Hamer, Lejla Bajic, Aleksandar Cejkov
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Publication number: 20180329723Abstract: Processing cores with the ability to suppress operations based on a contribution estimate for those operation for purposes of increasing the overall performance of the core are disclosed. Associated methods that can be conducted by such processing cores are also disclosed. One such method includes generating a reference value for a composite computation. A complete execution of the composite computation generates a precise output and requires execution of a set of component computations. The method also includes generating a component computation approximation. The method also includes evaluating the component computation approximation with the reference value. The method also includes executing a partial execution of the composite computation using the component computation approximation to produce an estimated output.Type: ApplicationFiled: May 10, 2018Publication date: November 15, 2018Applicant: Tenstorrent Inc.Inventors: Ljubisa Bajic, Milos Trajkovic, Ivan Hamer, Syed Gilani
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Publication number: 20180314946Abstract: A processing core for the efficient execution of a directed graph is disclosed. The processing core includes a memory and a first and a second data tile stored in the memory. The first and second data tiles include a first and a second set of data elements stored contiguously in the memory. The processing core also includes metadata relationally stored with the first data tile in the memory. The processing core also includes an execution engine, a control unit, and an instruction. Execution of the instruction uses the execution engine, a first data element in the first set of data elements, and a second data element in the second set of data elements. The control unit conditions execution of the instruction using the metadata. A standard execution of the instruction generates a standard output. A conditional execution of the instruction operation generates a conditionally executed output.Type: ApplicationFiled: April 26, 2018Publication date: November 1, 2018Applicant: Tenstorrent Inc.Inventors: Ljubisa Bajic, Milos Trajkovic, Ivan Hamer
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Publication number: 20180293486Abstract: Computer-implemented methods and associated hardware for executing directed graphs are disclosed herein. An example method includes deriving a simplified version of a directed graph, applying a pilot input tensor to the simplified version of the directed graph, and obtaining a collection of execution data during the application of the pilot input tensor to the simplified version of the directed graph. The method also includes applying a live input tensor to the directed graph and conditioning the execution of the directed graph using the collection of execution data. An output tensor is obtained from the conditional execution of the directed graph.Type: ApplicationFiled: April 4, 2018Publication date: October 11, 2018Applicant: Tenstorrent Inc.Inventors: Ljubisa Bajic, Milos Trajkovic, Ivan Hamer