Patents by Inventor Milton Clair Webb

Milton Clair Webb has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SELF-ALIGNED GATE EDGE AND LOCAL INTERCONNECT
    Publication number: 20230178594
    Abstract: Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.
    Type: Application
    Filed: December 20, 2022
    Publication date: June 8, 2023
    Inventors: Milton Clair Webb, Mark Bohr, Tahir Ghani, Szuya S. Liao
  • Self-aligned gate edge and local interconnect
    Patent number: 11563081
    Abstract: Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: January 24, 2023
    Assignee: Daedalus Prime LLC
    Inventors: Milton Clair Webb, Mark Bohr, Tahir Ghani, Szuya S. Liao
  • SELF-ALIGNED GATE EDGE AND LOCAL INTERCONNECT
    Publication number: 20200388675
    Abstract: Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Inventors: Milton Clair WEBB, Mark BOHR, Tahir GHANI, Szuya S. LIAO
  • Self-aligned gate edge and local interconnect
    Patent number: 10790354
    Abstract: Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Milton Clair Webb, Mark Bohr, Tahir Ghani, Szuya S. Liao
  • SELF-ALIGNED GATE EDGE AND LOCAL INTERCONNECT AND METHOD TO FABRICATE SAME
    Publication number: 20190326391
    Abstract: Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.
    Type: Application
    Filed: April 30, 2019
    Publication date: October 24, 2019
    Inventors: Milton Clair WEBB, Mark BOHR, Tahir GHANI, Szuya S. LIAO
  • Self-aligned gate edge and local interconnect and method to fabricate same
    Patent number: 10319812
    Abstract: Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Milton Clair Webb, Mark Bohr, Tahir Ghani, Szuya S. Liao
  • SELF-ALIGNED GATE EDGE AND LOCAL INTERCONNECT AND METHOD TO FABRICATE SAME
    Publication number: 20180047808
    Abstract: Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.
    Type: Application
    Filed: October 20, 2017
    Publication date: February 15, 2018
    Inventors: Milton Clair WEBB, Mark BOHR, Tahir GHANI, Szuya S. LIAO
  • Self-aligned gate edge and local interconnect and method to fabricate same
    Patent number: 9831306
    Abstract: Self-aligned gate edge and local interconnect structures and methods of fabricating self-aligned gate edge and local interconnect structures are described. In an example, a semiconductor structure includes a semiconductor fin disposed above a substrate and having a length in a first direction. A gate structure is disposed over the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate edge isolation structures is centered with the semiconductor fin. A first of the pair of gate edge isolation structures is disposed directly adjacent to the first end of the gate structure, and a second of the pair of gate edge isolation structures is disposed directly adjacent to the second end of the gate structure.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: November 28, 2017
    Assignee: Intel Corporation
    Inventors: Milton Clair Webb, Mark Bohr, Tahir Ghani, Szuya S. Liao