Patents by Inventor Milton Devon Miller, II
Milton Devon Miller, II has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7823028Abstract: An apparatus and computer instructions for interfacing with an operating system on a data processing system. Registers in a processor are allocated for use in providing a low-level console interface to a remote data processing system, wherein the registers are accessed by the remote data processing system using the low-level console interface. Data is exchanged with the remote data processing system through the low-level console interface. Also, multiple channels may be multiplexed through this low-level console interface.Type: GrantFiled: January 4, 2008Date of Patent: October 26, 2010Assignee: International Business Machines CorporationInventors: Anton Blanchard, Milton Devon Miller, II, Todd Alan Venton
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Patent number: 7805636Abstract: A data processing system and computer program product for analyzing data from a crash of the data processing system. A portion of the memory in the data processing system is preserved in response to the crash of the data processing system. The data processing system is rebooted with an environment suited for analyzing trace data in the portion of the memory.Type: GrantFiled: January 2, 2008Date of Patent: September 28, 2010Assignee: International Business Machines CorporationInventors: Anton Blanchard, Milton Devon Miller, II, Todd Alan Venton
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Patent number: 7743375Abstract: An information handling system includes instruction processing nodes in respective physical partitions. A communications bus couples two information processing nodes together. Each node includes hardware resources such as CPUs, memories and I/O adapters. Prior to a command to merge the physical partitions, the communication bus exhibits a disabled state such that the two information processing nodes are effectively disconnected. After receiving a command to merge the physical partitions, the system enables the communication bus to effectively hot-plug the two nodes together. A modified master hypervisor in one node stores data structures detailing the hardware resources of the two nodes. The modified master may assign resources from one node to a logical partition in another node.Type: GrantFiled: June 27, 2008Date of Patent: June 22, 2010Assignee: International Business Machines CorporationInventors: Benjiman Lee Goodman, Milton Devon Miller, II, Naresh Nayar
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Publication number: 20090327643Abstract: An information handling system includes instruction processing nodes in respective physical partitions. A communications bus couples two information processing nodes together. Each node includes hardware resources such as CPUs, memories and I/O adapters. Prior to a command to merge the physical partitions, the communication bus exhibits a disabled state such that the two information processing nodes are effectively disconnected. After receiving a command to merge the physical partitions, the system enables the communication bus to effectively hot-plug the two nodes together. A modified master hypervisor in one node stores data structures detailing the hardware resources of the two nodes. The modified master may assign resources from one node to a logical partition in another node.Type: ApplicationFiled: June 27, 2008Publication date: December 31, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Benjiman Lee Goodman, Milton Devon Miller, II, Naresh Nayar
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Patent number: 7536539Abstract: A method, apparatus and computer instructions for discovering hardware nodes having a hierarchical organization. A subset of the hardware nodes in the data processing system is initialized prior to loading an operating system supporting parallel threads. In response to loading the operating system, thread for each hardware node discovered below a known hardware node is created to form a set of threads.Type: GrantFiled: August 5, 2004Date of Patent: May 19, 2009Assignee: International Business Machines CorporationInventors: Anton Blanchard, Milton Devon Miller, II, Todd Alan Venton
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Patent number: 7401262Abstract: A method, apparatus and computer instructions for interfacing with an operating system on a data processing system. Registers in a processor are allocated for use in providing a low-level console interface to a remote data processing system, wherein the registers are accessed by the remote data processing system using the low-level console interface. Data is exchanged with the remote data processing system through the low-level console interface. Also, multiple channels may be multiplexed through this low-level console interface.Type: GrantFiled: August 5, 2004Date of Patent: July 15, 2008Assignee: International Business Machines CorporationInventors: Anton Blanchard, Milton Devon Miller, II, Todd Alan Venton
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Patent number: 7346809Abstract: A method, apparatus, and computer instructions for analyzing data from a crash of the data processing system. A portion of the memory in the data processing system is preserved in response to the crash of the data processing system. The data processing system is rebooted with an environment suited for analyzing trace data in the portion of the memory.Type: GrantFiled: August 5, 2004Date of Patent: March 18, 2008Assignee: International Business Machines CorporationInventors: Anton Blanchard, Milton Devon Miller, II, Todd Alan Venton
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Patent number: 7272759Abstract: A method, apparatus, and computer instructions for monitoring a device in a data processing system. A register associated with the device is accessed from a reduced function processor core through a connection between the register for the device and the reduced function processor core. The device is monitored using the value of the register.Type: GrantFiled: August 5, 2004Date of Patent: September 18, 2007Assignee: International Business Machines CorporationInventors: Anton Blanchard, Milton Devon Miller, II, Todd Alan Venton
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Patent number: 7146515Abstract: A system, method, and computer program product are disclosed for executing a reliable warm reboot of one of multiple partitions included in a logically partitioned data processing system. The data processing system includes partition hardware. A request to reboot a particular partition is received within the partition where the particular partition includes multiple processors. Prior to executing the reboot request, the partition hardware is set to a predetermined state. The reboot request is then executed within the particular partition. The predetermined state is preferably achieved by resetting the partition hardware to a predetermined state.Type: GrantFiled: June 20, 2002Date of Patent: December 5, 2006Assignee: International Business Machines CorporationInventors: Bradley Ryan Harrington, Chetan Mehta, Milton Devon Miller, II, Michael Anthony Perez, David Lee Randall, David R. Willoughby
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Patent number: 6898731Abstract: A system, method, and computer program product are disclosed for preventing machine crashes due to hard errors in one of multiple, different processors that are included in a logically partitioned data processing system. An error occurring in one of the processors is detected. A determination is then made regarding whether the processor has been deconfigured. The partition is then rebooted only in response to a determination that the processor has been deconfigured and will not be included in the partition processor resources. Thus, only the configured processors are rebooted. The deconfigured processor is not rebooted.Type: GrantFiled: January 10, 2002Date of Patent: May 24, 2005Assignee: International Business Machines CorporationInventors: Mark Elliott Hack, Alongkorn Kitamorn, Gordon D. McIntosh, Milton Devon Miller, II, Kanisha Patel, David Lee Randall
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Patent number: 6845470Abstract: A method and system for identifying a source of a corrupt data in a memory in a multiprocessor computer system. When a computer program stores corrupt data causing a program failure or a system crash, the corrupt data and its address are identified. The multiprocessor computer system is shut down, and the corrupt data is cleared from the memory. Before fully re-booting the multiprocessor computer system, a processor is selected from the multiprocessor computer system to load and run monitor code designed to monitor the location where the corrupt data was stored. The program that previously stored the corrupt data is restarted, and the selected processor detects any re-storage of the corrupt data in the same memory address. All processors in the computer system are then immediately suspended. The registers of all processors suspected of storing corrupt data are inspected to determine the source of the corrupt data.Type: GrantFiled: February 27, 2002Date of Patent: January 18, 2005Assignee: International Business Machines CorporationInventors: Christopher Harry Austen, Van Hoa Lee, Milton Devon Miller, II, Douglas Wayne Oliver
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Patent number: 6526496Abstract: A burst transfer alignment apparatus and method are provided. An interface between the word-aligned subsystem and the double-word-aligned system bus loads a predetermined invalid bit pattern on the system bus corresponding to the second word of the double-word access, in response to a misaligned read. When execution of the predetermined invalid pattern is attempted, an execution exception is thrown. In response the cache line containing the invalid pattern giving rise to the exception is invalidated at the address of the invalid instruction data. Returning from the exception to the address of the invalid pattern, the cache line is refetched. The refetch occurs on an even word boundary, and therefore the refetched cache line transfers properly because the even word address coincides with a double word boundary expected by the bus system.Type: GrantFiled: October 21, 1999Date of Patent: February 25, 2003Assignee: International Business Machines CorporationInventors: Steven Paul Hartman, Van Hoa Lee, Milton Devon Miller, II