Abstract: A first fin structure is disposed over a substrate. The first fin structure contains a semiconductor material. A gate dielectric layer is disposed over upper and side surfaces of the first fin structure. A gate electrode layer is formed over the gate dielectric layer. A second fin structure is disposed over the substrate. The second fin structure is physically separated from the first fin structure and contains a ferroelectric material. The second fin structure is electrically coupled to the gate electrode layer.

Abstract: A multi-procedure integrated automatic production line for hard alloy blades under robot control is provided. The production line includes a rail-guided robot. A cutter passivation device and a blade cleaning and drying device are arranged on one side of the rail-guided robot. A blade-coating transfer table, a blade coating device, a blade boxing transfer table, a blade-tooling dismounting device and a blade boxing device are sequentially arranged on another side of the rail-guided robot. The blade-tooling dismounting device is arranged on one side of the blade boxing transfer table. The production line further includes squirrel-cage toolings for carrying the blades. The squirrel-cage tooling that are loaded with the blades can run among the cutter passivation device, the blade cleaning and drying device, the blade-coating transfer table and the blade boxing transfer table. The blades after being treated through the blade-tooling dismounting device are sent to the blade boxing device.

Abstract: The present application relates to a top plate jacking device and jacking construction method configured for V-shaped columns, the top plate jacking device comprising a temporary support pile comprises a plurality of pile holes arranged on a construction surface, a bottom end of the pile hole is cast-in-place with a bearing platform, a temporary support column is inserted on the bearing platform, a plurality of pillars are fixed at a top of the temporary support column, wherein comprises a plurality of vertically connected column segments, two adjacent column segments detachably connected vertically through a connecting component; a support block is provided at a top of the plurality of pillars, the top of the support block abuts against a lower surface of the top plate; a hydraulic jack is configured to jack the top plate and is provided with a plurality of intervals at the top of the temporary support column.

Abstract: The present disclosure discloses a high-safety ternary positive electrode material and a method for preparing the same; wherein the ternary positive electrode material has a chemical composition of Lia(NixCoyMn1-x-y)1-bMbO2-cAc, wherein 0.75?a?1.2, 0.75?x<1, 0<y?0.15, 1?x?y>0, 0?b?0.01, 0?c?0.2, M is one or more selected from the group consisting of Al, Zr, Ti, Y, Sr, W and Mg, and A is one or more selected from the group consisting of S, F and N; and CMn?(1?x?y)?0.07; CCo?y?0.05; 0?[CMn?(1?x?y)]/(CCo?y)?2.0. The ternary positive electrode material of the present disclosure is a high-nickel single crystal material with gradient concentration; it has the advantages of high capacity and high thermal stability, and the preparation method is simple, and is suitable for large-scale production.

Abstract: The present invention relates to a powder dry-pressing molding device and method.

Abstract: A traveling roller includes a left roller, a right roller, a support shaft, a driving device and a sealing device, wherein the traveling roller may also include an intermediate roller; the support shaft is provided on an axis of the left and right rollers; inner walls of the left and right rollers are respectively connected to support plates; an outer ring of each of the support plates is provided with a notch for dust to flow out; the driving device includes an outer rotor motor sleeved on the support shaft; transmission devices are provided between two end cap seats of a rotor body of the outer rotor motor and the support plates; pawl members of the transmission devices are fixedly sleeved on the end cap seats, or driving planetary gears of the transmission devices are fixed to the rotor body.

Abstract: An apparatus includes a memory and a processor. The memory stores descriptions of known vulnerabilities and information generated by a monitoring subsystem. Each description of a known vulnerability identifies software components that are associated with the known vulnerability. The monitoring subsystem monitors software programs that are installed within a computer system. The information includes descriptions of issues that are associated with the software programs. The processor generates a set of mappings, based on a comparison between the text describing the known software vulnerabilities and the text describing the issues. Each mapping associates a software program that is associated with an issue with a known software vulnerability. The processor also uses a machine learning algorithm to predict that a given software program is associated with a particular software vulnerability.

Abstract: Embodiments of the present disclosure provide a flexible display panel and a manufacturing method thereof, wherein the flexible display panel includes: an array substrate; an organic light emitting layer disposed on the array substrate; a dam disposed on the array substrate and disposed to surround the organic light emitting layer; and an encapsulation layer covering the organic light emitting layer and the dam, wherein the dam comprises a first side surface close to the organic light emitting layer, and a second side surface away from the organic light emitting layer, and the second side surface is disposed with at least one of a groove, a stepped structure, or a sharp corner structure.

Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base. The semiconductor device structure includes a first multilayer stack over the base. The first multilayer stack includes a first channel layer and a second channel layer over and spaced apart from the first channel layer. The semiconductor device structure includes a gate stack over the substrate. The gate stack wraps around the first multilayer stack. The semiconductor device structure includes an inner spacer layer between the second channel layer and the first channel layer and between the first channel layer and the base. The semiconductor device structure includes a bottom spacer over the base. The semiconductor device structure includes a first source/drain structure over the bottom spacer and connected to the second channel layer.

Abstract: An adhesive tape that includes: a first adhesive layer defining an upper surface of the tape; a second adhesive layer defining a lower surface of the tape; and a reinforcement layer (or first and second reinforcement layers) and a thermally activated layer between the first adhesive layer and the second adhesive layer. The thermally activated layer is a thermoplastic polymer layer. The thermoplastic layer may be made of ethylene-vinyl acetate copolymer, modified polyolefin, ethylene acrylic acid copolymer, ethylene terpolymer, polyamide copolymer, poly(trans-1,4-isoprene), polyethylene oxide, or a combination thereof. Further, the thermoplastic layer may exhibit a melting point from 60° C. to 150° C. and may have a molecular weight from 1,000 to 1,000,000.

Abstract: Aspects of the disclosure relate to multi-factor user authentication for card-based payment transactions using blockchain tokens. An computing platform may receive, from a computing device, transaction details associated with a card-based payment transaction corresponding to a user, wherein the transaction details comprise a card number of a payment card. The computing platform may determine, based on the card number, a user device associated with the user. The computing platform may send, to the user device, a one-time passcode (OTP). After sending the OTP, the computing platform may receive a security key. The security key may be generated based on the sent OTP and a blockchain token hash. The computing platform may, based on the received security key, send, to the computing device, a message indicating whether the transaction is approved or declined.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.

Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer.

Abstract: The disclosed circuit includes a first and a second active region (AR) spaced a spacing S along a direction in a first standard cell (SC) that spans Dl along the direction between a first and a second cell edge (CE). Each of the first and second ARs spans a first width W1 along the direction; a third and a fourth AR spaced S in a second SC that spans a second dimension Ds along the direction between a third and a fourth CE; and gate stacks extend from the fourth CE of the second SC to the first CE of the first SC, wherein Ds<Dl; each of the third and fourth ARs spans a second width W2 along the direction; W2<W1; and the third CE is aligned with and contacts the second CE. The first and second ARs have a structure different from the third and fourth ARs.

Abstract: Various embodiments of the present application are directed towards a bipolar selector having independently tunable threshold voltages, as well as a memory cell comprising the bipolar selector and a memory array comprising the memory cell. In some embodiments, the bipolar selector comprises a first unipolar selector and a second unipolar selector. The first and second unipolar selectors are electrically coupled in parallel with opposite orientations and may, for example, be diodes or some other suitable unipolar selectors. By placing the first and second unipolar selectors in parallel with opposite orientations, the first unipolar selector independently defines a first threshold voltage of the bipolar selector and the second unipolar selector independently defines a second threshold voltage of the bipolar selector. As a result, the first and second threshold voltages can be independently tuned by adjusting parameters of the first and second unipolar selectors.

Abstract: Various embodiments of the present application are directed towards a bipolar selector having independently tunable threshold voltages, as well as a memory cell comprising the bipolar selector and a memory array comprising the memory cell. In some embodiments, the bipolar selector comprises a first unipolar selector and a second unipolar selector. The first and second unipolar selectors are electrically coupled in parallel with opposite orientations and may, for example, be diodes or some other suitable unipolar selectors. By placing the first and second unipolar selectors in parallel with opposite orientations, the first unipolar selector independently defines a first threshold voltage of the bipolar selector and the second unipolar selector independently defines a second threshold voltage of the bipolar selector. As a result, the first and second threshold voltages can be independently tuned by adjusting parameters of the first and second unipolar selectors.

Abstract: The disclosed circuit includes a first and a second active region (AR) spaced a spacing S along a direction in a first standard cell (SC) that spans Dl along the direction between a first and a second cell edge (CE). Each of the first and second ARs spans a first width W1 along the direction; a third and a fourth AR spaced S in a second SC that spans a second dimension Ds along the direction between a third and a fourth CE; and gate stacks extend from the fourth CE of the second SC to the first CE of the first SC, wherein Ds<Dl; each of the third and fourth ARs spans a second width W2 along the direction; W2<W1; and the third CE is aligned with and contacts the second CE. The first and second ARs have a structure different from the third and fourth ARs.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a <100> crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a <110> crystalline direction along the first direction.