Patents by Inventor Min-Feng KU
Min-Feng KU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240036108Abstract: A socket of a testing tool is configured to provide testing signals. A device-under-test (DUT) board is configured to provide electrical routing. An integrated circuit (IC) die is disposed between the socket and the DUT board. The testing signals are electrically routed to the IC die through the DUT board. The IC die includes a substrate in which plurality of transistors is formed. A first structure contains a plurality of first metallization components. A second structure contains a plurality of second metallization components. The first structure is disposed over a first side of the substrate. The second structure is disposed over a second side of the substrate opposite the first side. A trench extends through the DUT board and extends partially into the IC die from the second side. A signal detection tool is configured to detect electrical or optical signals generated by the IC die.Type: ApplicationFiled: March 30, 2023Publication date: February 1, 2024Inventors: Chien-Yi Chen, Kao-Chih Liu, Chia Hong Lin, Yu-Ting Lin, Min-Feng Ku
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Publication number: 20230187315Abstract: An exemplary semiconductor structure includes a device substrate having a first side and a second side. A dielectric layer is disposed over the first side of the device substrate. A through via extends along a first direction through the dielectric layer and through the device substrate from the first side to the second side. The through via has a total length along the first direction and a width along a second direction that is different than the first direction. The total length is a sum of a first length of the through via in the dielectric layer and a second length of the through via in the device substrate. The first length is less than the second length. A guard ring is disposed in the dielectric layer and around the through via.Type: ApplicationFiled: June 6, 2022Publication date: June 15, 2023Inventors: Min-Feng Ku, Yao-Chun Chuang, Cheng-Chien Li, Ching-Pin Lin
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Publication number: 20230178589Abstract: An exemplary semiconductor structure includes a device substrate having a first side and a second side. A dielectric layer is disposed over the first side of the device substrate. A through via extends along a first direction through the dielectric layer and through the device substrate from the first side to the second side. A guard ring is disposed in the dielectric layer and around the through via. The guard ring includes metal layers stacked along the first direction. The metal layers include first sidewalls and second sidewall. The first sidewalls form an inner sidewall of the guard ring. An overlap between the first sidewalls of the metal layers is less than about 10 nm. The overlap is along a second direction different than the first direction.Type: ApplicationFiled: June 3, 2022Publication date: June 8, 2023Inventors: Min-Feng Ku, Yao-Chun Chuang, Cheng-Chien Li, Ching-Pin Lin
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Publication number: 20220254739Abstract: A semiconductor article which includes a semiconductor substrate, a back end of the line (BEOL) wiring portion on the semiconductor substrate, a through silicon via and a guard ring. The semiconductor substrate is made of a semiconductor material. The BEOL wiring portion includes a plurality of wiring layers having electrically conductive wiring and electrical insulating material. The through silicon via provides a conductive path through the BEOL wiring portion and the semiconductor substrate. The guard ring surrounds the through silicon via in the BEOL wiring portion and in some embodiments in the semiconductor substrate.Type: ApplicationFiled: September 21, 2021Publication date: August 11, 2022Inventors: Min-Feng KU, Yao-Chun CHUANG, Ching-Pin LIN, Cheng-Chien LI
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Patent number: 9929070Abstract: A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is disposed under the first package component and molded to the first and the second package components, wherein the molding material and the first package component form an interface. An isolation region includes a first edge, wherein the first edge of the isolation region contacts a first edge of the first package component and a first edge of the molding material. The isolation has a bottom lower than the interface.Type: GrantFiled: December 22, 2016Date of Patent: March 27, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Horng Chang, Tin-Hao Kuo, Tsung-Fu Tsai, Min-Feng Ku
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Publication number: 20170103933Abstract: A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is disposed under the first package component and molded to the first and the second package components, wherein the molding material and the first package component form an interface. An isolation region includes a first edge, wherein the first edge of the isolation region contacts a first edge of the first package component and a first edge of the molding material. The isolation has a bottom lower than the interface.Type: ApplicationFiled: December 22, 2016Publication date: April 13, 2017Inventors: Chih-Horng Chang, Tin-Hao Kuo, Tsung-Fu Tsai, Min-Feng Ku
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Patent number: 9548245Abstract: A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is disposed under the first package component and molded to the first and the second package components, wherein the molding material and the first package component form an interface. An isolation region includes a first edge, wherein the first edge of the isolation region contacts a first edge of the first package component and a first edge of the molding material. The isolation has a bottom lower than the interface.Type: GrantFiled: May 29, 2015Date of Patent: January 17, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Horng Chang, Tin-Hao Kuo, Tsung-Fu Tsai, Min-Feng Ku
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Publication number: 20150262882Abstract: A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is disposed under the first package component and molded to the first and the second package components, wherein the molding material and the first package component form an interface. An isolation region includes a first edge, wherein the first edge of the isolation region contacts a first edge of the first package component and a first edge of the molding material. The isolation has a bottom lower than the interface.Type: ApplicationFiled: May 29, 2015Publication date: September 17, 2015Inventors: Chih-Horng Chang, Tin-Hao Kuo, Tsung-Fu Tsai, Min-Feng Ku
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Patent number: 9048333Abstract: A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is disposed under the first package component and molded to the first and the second package components, wherein the molding material and the first package component form an interface. An isolation region includes a first edge, wherein the first edge of the isolation region contacts a first edge of the first package component and a first edge of the molding material. The isolation has a bottom lower than the interface.Type: GrantFiled: February 25, 2014Date of Patent: June 2, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Horng Chang, Tin-Hao Kuo, Tsung-Fu Tsai, Min-Feng Ku
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Publication number: 20140179062Abstract: A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is disposed under the first package component and molded to the first and the second package components, wherein the molding material and the first package component form an interface. An isolation region includes a first edge, wherein the first edge of the isolation region contacts a first edge of the first package component and a first edge of the molding material. The isolation has a bottom lower than the interface.Type: ApplicationFiled: February 25, 2014Publication date: June 26, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Horng Chang, Tin-Hao Kuo, Tsung-Fu Tsai, Min-Feng Ku
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Patent number: 8710681Abstract: A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is disposed under the first package component and molded to the first and the second package components, wherein the molding material and the first package component form an interface. An isolation region includes a first edge, wherein the first edge of the isolation region contacts a first edge of the first package component and a first edge of the molding material. The isolation has a bottom lower than the interface.Type: GrantFiled: May 31, 2012Date of Patent: April 29, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Horng Chang, Tin-Hao Kuo, Tsung-Fu Tsai, Min-Feng Ku
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Publication number: 20130320572Abstract: A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is disposed under the first package component and molded to the first and the second package components, wherein the molding material and the first package component form an interface. An isolation region includes a first edge, wherein the first edge of the isolation region contacts a first edge of the first package component and a first edge of the molding material. The isolation has a bottom lower than the interface.Type: ApplicationFiled: May 31, 2012Publication date: December 5, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Horng Chang, Tin-Hao Kuo, Tsung-Fu Tsai, Min-Feng Ku
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Patent number: 8581399Abstract: A semiconductor device comprises a substrate comprising a major surface and a plurality of metal bumps on the major surface. Each of the plurality of metal bumps comprises a metal via on the major surface and a metal pillar on the metal via having an overlay offset between the metal pillar and metal via. A first metal bump of the metal bumps has a first overlay offset and a second metal bump of the metal bumps farther than the first metal bump to a centroid of the substrate has a second overlay offset greater than the first overlay offset.Type: GrantFiled: July 28, 2011Date of Patent: November 12, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Fu Tsai, Min-Feng Ku, Yian-Liang Kuo
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Publication number: 20130026621Abstract: A semiconductor device comprises a substrate comprising a major surface and a plurality of metal bumps on the major surface. Each of the plurality of metal bumps comprises a metal via on the major surface and a metal pillar on the metal via having an overlay offset between the metal pillar and metal via. A first metal bump of the metal bumps has a first overlay offset and a second metal bump of the metal bumps farther than the first metal bump to a centroid of the substrate has a second overlay offset greater than the first overlay offset.Type: ApplicationFiled: July 28, 2011Publication date: January 31, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Fu TSAI, Min-Feng KU, Yian-Liang KUO