Abstract: As inputs of a controller of a direct current (DC)-DC converter are sampled for a predetermined time and thus two-dimensional state information in which one axis is an input physical quantity and the other axis is a time is generated, the two-dimensional state information is processed by a convolutional neural network to determine and output one of a plurality of control signals. An artificial intelligence control part may operate in accordance with a plurality of operation conditions or dynamically determined operation conditions by applying different artificial intelligence engines according to operation modes.

Abstract: Provided is a method for reading data from a nonvolatile memory device. In the method, a read method includes a first read step including reading a first memory cell of the nonvolatile memory device by applying a first set of read voltages to the first memory cell. The read method further includes a second read step including reading the first memory cell by applying a second set of read voltages and none of the voltages in the first set to the first memory cell when it is determined that the first read step results in an error and cannot be corrected with error correction. The second read step is performed by using data resulting from the first read step.

Abstract: Provided is a method for reading data from a nonvolatile memory device. In the method, a read method includes a first read step including reading a first memory cell of the nonvolatile memory device by applying a first set of read voltages to the first memory cell. The read method further includes a second read step including reading the first memory cell by applying a second set of read voltages and none of the voltages in the first set to the first memory cell when it is determined that the first read step results in an error and cannot be corrected with error correction. The second read step is performed by using data resulting from the first read step.

Abstract: Provided is a method for reading data from a nonvolatile memory device. In the method, a read method includes a first read step including reading a first memory cell of the nonvolatile memory device by applying a first set of read voltages to the first memory cell. The read method further includes a second read step including reading the first memory cell by applying a second set of read voltages and none of the voltages in the first set to the first memory cell when it is determined that the first read step results in an error and cannot be corrected with error correction. The second read step is performed by using data resulting from the first read step.

Abstract: A nonvolatile memory device comprises a memory core and a controller for controlling the wear level of a memory block in the nonvolatile memory device. The controller determines the wear level of a memory block by obtaining data of an actual wear level from a charge measurement cell of a selected region of the memory cell, and stores the wear level of the selected region in an erase count table.

Abstract: Provided is a method for reading data from a nonvolatile memory device. In the method, a read method includes a first read step including reading a first memory cell of the nonvolatile memory device by applying a first set of read voltages to the first memory cell. The read method further includes a second read step including reading the first memory cell by applying a second set of read voltages and none of the voltages in the first set to the first memory cell when it is determined that the first read step results in an error and cannot be corrected with error correction. The second read step is performed by using data resulting from the first read step.

Abstract: A flash memory device including a high voltage generator circuit that is adapted to supply a program voltage having a target voltage to a selected word line is provided. The flash memory device is adapted to terminate the program interval in accordance with when the program voltage has been restored to the target voltage after dropping below the target voltage. A method for operating the flash memory device is also provided.

Abstract: A nonvolatile memory device comprises a memory core and a controller for controlling the wear level of a memory block in the nonvolatile memory device. The controller determines the wear level of a memory block by obtaining data of an actual wear level from a charge measurement cell of a selected region of the memory cell, and stores the wear level of the selected region in an erase count table.

Abstract: A method is provided for verifying a programming operation of a flash memory device. The flash memory device includes at least one memory string in which a string selection transistor, multiple memory cells and a ground selection transistor are connected in series, and the programming operation is performed with respect to a selected memory cell in the memory string. The method includes applying a voltage, obtained by adding a threshold voltage of the string selection transistor to a power supply voltage, to a string selection line connected to the string selection transistor; applying a ground voltage to wordlines connected to each of the memory cells and a ground selection line connected to the ground selection transistor; precharging a bitline connected to the memory string to the power supply voltage; and determining whether a programming operation of the selected memory cell is complete.

Abstract: A flash memory device comprising a high voltage generator circuit that is adapted to supply a program voltage having a target voltage to a selected word line is provided. The flash memory device is adapted to terminate the program interval in accordance with when the program voltage has been restored to the target voltage after dropping below the target voltage. A method for operating the flash memory device is also provided.

Abstract: A non-volatile semiconductor memory device may include a memory cell array and a controller coupled to the memory cell array. The memory cell array may include first and second memory cells coupled to respective first and second word lines. Each of the first and second memory cells may be configured to be programmed to one of a first, a second, or a third threshold voltage so that the first and second memory cells provide nine different threshold voltage combinations. The controller may be configured to provide a mapping of data of a set of three binary bits providing eight different data combinations to eight of the nine different threshold voltage combinations provided by the first and second memory cells. The controller may be further configured to write data of first, second, and third binary bits to the first and second memory cells by programming each of the first and second memory cells to a respective one of the first, second, or third threshold voltages using the mapping of data.

Abstract: A non-volatile semiconductor memory device includes a page buffer comprising a lower latch block and an upper latch block, and a memory array that is connected to the lower latch block via a lower common bit line and that is connected to the upper latch block via an upper common bit line. The memory array includes a plurality of non-volatile memory cells, a lower even bit line and a lower odd bit line that are selectively connectable to the lower common bit line, an upper even bit line and an upper odd bit line that are selectively connectable to the upper common bit line, a first switch that electrically connects the lower even bit line to the upper even bit line in response to a first connection control signal and a second switch that electrically connects the lower odd bit line to the upper odd bit line in response to a second connection control signal.

Abstract: A flash memory device comprising a high voltage generator circuit that is adapted to supply a program voltage having a target voltage to a selected word line is provided. The flash memory device is adapted to terminate the program interval in accordance with when the program voltage has been restored to the target voltage after dropping below the target voltage. A method for operating the flash memory device is also provided.

Abstract: A non-volatile semiconductor memory device includes a page buffer comprising a lower latch block and an upper latch block, and a memory array that is connected to the lower latch block via a lower common bit line and that is connected to the upper latch block via an upper common bit line. The memory array includes a plurality of non-volatile memory cells, a lower even bit line and a lower odd bit line that are selectively connectable to the lower common bit line, an upper even bit line and an upper odd bit line that are selectively connectable to the upper common bit line, a first switch that electrically connects the lower even bit line to the upper even bit line in response to a first connection control signal and a second switch that electrically connects the lower odd bit line to the upper odd bit line in response to a second connection control signal.

Abstract: A method is provided for verifying a programming operation of a flash memory device. The flash memory device includes at least one memory string in which a string selection transistor, multiple memory cells and a ground selection transistor are connected in series, and the programming operation is performed with respect to a selected memory cell in the memory string. The method includes applying a voltage, obtained by adding a threshold voltage of the string selection transistor to a power supply voltage, to a string selection line connected to the string selection transistor; applying a ground voltage to wordlines connected to each of the memory cells and a ground selection line connected to the ground selection transistor; precharging a bitline connected to the memory string to the power supply voltage; and determining whether a programming operation of the selected memory cell is complete.

Abstract: In a nonvolatile memory device, a first verification result indicates whether a block of memory cells has been successfully programmed and a second verification result indicates whether a far cell in the block has been is successfully programmed. A controller defines the level and application time for the program voltage applied during a next program loop in response to the first and second verification results.

Abstract: A flash memory data storage apparatus comprises a flash memory and a flash interface. The flash memory transceives data through a flash bus group. The flash interface includes first through n'th flash input buffers that transfer data to a host bus group in stages in response to first through n'th transfer clock control signals. An i'th flash input buffer provides data through i'th input-buffer bus groups in number of at least Ni. A bus width of each of the i'th input-buffer bus groups is wider than a bus width of each of an (i?l)'th input-buffer bus groups. A period of an i'th transfer clock control signal is longer than a period of an (i?1)'th transfer clock control signal. The Ni is obtained by dividing a bus width of the flash bus group by dividing the bus width of the flash bus group by the bus width of the each of the i'th input-buffer bus groups.

Abstract: Some embodiments of the present invention provide programming operations for reducing a program time for a nonvolatile memory device. A nonvolatile semiconductor memory device is programmed by receiving data to be programmed into memory cells from a host, programming the data into the memory cells, performing a verify read operation to determine whether the data has been successfully programmed into the memory cells, and performing a Y-scan operation while performing the verify read operation to sequentially scan and output data read from bit lines coupled to the memory cells.

Abstract: A non-volatile memory device performs a multi-page copyback operation where after a plurality of copyback data read out from one or more mats are sequentially stored in a plurality of buffers, the stored data are simultaneously programmed to different mats. The copyback data may be read out without limitation to the location of mats and the number of copyback data to be read out from the respective mats. The read-out copyback data are simultaneously programmed to a plurality of mats.

Abstract: In a nonvolatile memory device, a first verification result indicates whether a block of memory cells has been successfully programmed and a second verification result indicates whether a far cell in the block has been is successfully programmed. A controller defines the level and application time for the program voltage applied during a next program loop in response to the first and second verification results.