Patents by Inventor Min-Hsiung Chiang
Min-Hsiung Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9899263Abstract: A method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The plurality of gate structure layout patterns has a predetermined pitch smaller than a spatial resolution of a predetermined lithographic technology. A first layout pattern of the set of layout patterns has a width less than twice the predetermined pitch.Type: GrantFiled: May 9, 2016Date of Patent: February 20, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung-Heng Hsieh, Chung-Te Lin, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Min-Hsiung Chiang, Ting-Wei Chiang, Li-Chun Tien
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Patent number: 9691721Abstract: A device includes an active region in a semiconductor substrate, a gate strip over and crossing the active region, and a jog over the active region and connected to the gate strip to form a continuous region. The jog is on a side of the gate strip. A first contact plug is at a same level as the gate strip, wherein the first contact plug is on the side of the gate strip. A second contact plug is over the jog and the first contact plug. The second contact plug electrically interconnects the first contact plug and the jog.Type: GrantFiled: May 27, 2016Date of Patent: June 27, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Lin Wu, Tung-Heng Hsieh, Jiun-Ming Kuo, Min-Hsiung Chiang, Che-Yuan Hsu
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Patent number: 9570584Abstract: Some embodiments of the present disclosure provide a semiconductor device including a substrate and a gate structure on the substrate. A first well region of a first conductivity type is in the substrate, close to a first sidewall of the gate structure. A second well region of a second conductivity type is also in the substrate close to the second sidewall of the gate structure. A conductive region is disposed in the second well region. The conductive region can be an epitaxy region. A chemical composition inside the second well region between the conductive region and the gate structure is essentially homogeneous as a chemical composition throughout the second well region.Type: GrantFiled: August 14, 2014Date of Patent: February 14, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chih Hsiung Lin, Chia-Der Chang, Pin-Cheng Hsu, Min-Hsiung Chiang, Shu-Wei Chung, Hao Wen Hsu
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Publication number: 20160276297Abstract: A device includes an active region in a semiconductor substrate, a gate strip over and crossing the active region, and a jog over the active region and connected to the gate strip to form a continuous region. The jog is on a side of the gate strip. A first contact plug is at a same level as the gate strip, wherein the first contact plug is on the side of the gate strip. A second contact plug is over the jog and the first contact plug. The second contact plug electrically interconnects the first contact plug and the jog.Type: ApplicationFiled: May 27, 2016Publication date: September 22, 2016Inventors: Tsung-Lin Wu, Tung-Heng Hsieh, Jiun-Ming Kuo, Min-Hsiung Chiang, Che-Yuan Hsu
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Publication number: 20160254190Abstract: A method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The plurality of gate structure layout patterns has a predetermined pitch smaller than a spatial resolution of a predetermined lithographic technology. A first layout pattern of the set of layout patterns has a width less than twice the predetermined pitch.Type: ApplicationFiled: May 9, 2016Publication date: September 1, 2016Inventors: Tung-Heng Hsieh, Chung-Te Lin, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Min-Hsiung Chiang, Ting-Wei Chiang, Li-Chun Tien
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Patent number: 9355912Abstract: A device includes an active region in a semiconductor substrate, a gate strip over and crossing the active region, and a jog over the active region and connected to the gate strip to form a continuous region. The jog is on a side of the gate strip. A first contact plug is at a same level as the gate strip, wherein the first contact plug is on the side of the gate strip. A second contact plug is over the jog and the first contact plug. The second contact plug electrically interconnects the first contact plug and the jog.Type: GrantFiled: December 1, 2014Date of Patent: May 31, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Lin Wu, Tung-Heng Hsieh, Jiun-Ming Kuo, Min-Hsiung Chiang, Che-Yuan Hsu
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Patent number: 9336348Abstract: A method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The plurality of gate structure layout patterns has a predetermined pitch smaller than a spatial resolution of a predetermined lithographic technology. A first layout pattern of the set of layout patterns has a width less than twice the predetermined pitch.Type: GrantFiled: September 12, 2014Date of Patent: May 10, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung-Heng Hsieh, Chung-Te Lin, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Min-Hsiung Chiang, Ting-Wei Chiang, Li-Chun Tien
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Publication number: 20160078164Abstract: A method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The plurality of gate structure layout patterns has a predetermined pitch smaller than a spatial resolution of a predetermined lithographic technology. A first layout pattern of the set of layout patterns has a width less than twice the predetermined pitch.Type: ApplicationFiled: September 12, 2014Publication date: March 17, 2016Inventors: Tung-Heng HSIEH, Chung-Te LIN, Sheng-Hsiung WANG, Hui-Zhong ZHUANG, Min-Hsiung CHIANG, Ting-Wei CHIANG, Li-Chun TIEN
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Publication number: 20160049464Abstract: Some embodiments of the present disclosure provide a semiconductor device including a substrate and a gate structure on the substrate. A first well region of a first conductivity type is in the substrate, close to a first sidewall of the gate structure. A second well region of a second conductivity type is also in the substrate close to the second sidewall of the gate structure. A conductive region is disposed in the second well region. The conductive region can be an epitaxy region. A chemical composition inside the second well region between the conductive region and the gate structure is essentially homogeneous as a chemical composition throughout the second well region.Type: ApplicationFiled: August 14, 2014Publication date: February 18, 2016Inventors: CHIH HSIUNG LIN, CHIA-DER CHANG, PIN-CHENG HSU, MIN-HSIUNG CHIANG, SHU-WEI CHUNG, HAO WEN HSU
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Publication number: 20150087143Abstract: A device includes an active region in a semiconductor substrate, a gate strip over and crossing the active region, and a jog over the active region and connected to the gate strip to form a continuous region. The jog is on a side of the gate strip. A first contact plug is at a same level as the gate strip, wherein the first contact plug is on the side of the gate strip. A second contact plug is over the jog and the first contact plug. The second contact plug electrically interconnects the first contact plug and the jog.Type: ApplicationFiled: December 1, 2014Publication date: March 26, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Lin Wu, Tung-Heng Hsieh, Jiun-Ming Kuo, Min-Hsiung Chiang, Che-Yuan Che
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Patent number: 8901627Abstract: A device includes an active region in a semiconductor substrate, a gate strip over and crossing the active region, and a jog over the active region and connected to the gate strip to form a continuous region. The jog is on a side of the gate strip. A first contact plug is at a same level as the gate strip, wherein the first contact plug is on the side of the gate strip. A second contact plug is over the jog and the first contact plug. The second contact plug electrically interconnects the first contact plug and the jog.Type: GrantFiled: November 16, 2012Date of Patent: December 2, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Lin Wu, Tung-Heng Hsieh, Jiun-Ming Kuo, Min-Hsiung Chiang, Che-Yuan Che
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Publication number: 20140138750Abstract: A device includes an active region in a semiconductor substrate, a gate strip over and crossing the active region, and a jog over the active region and connected to the gate strip to form a continuous region. The jog is on a side of the gate strip. A first contact plug is at a same level as the gate strip, wherein the first contact plug is on the side of the gate strip. A second contact plug is over the jog and the first contact plug. The second contact plug electrically interconnects the first contact plug and the jog.Type: ApplicationFiled: November 16, 2012Publication date: May 22, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Lin Wu, Tung-Heng Hsieh, Jiun-Ming Kuo, Min-Hsiung Chiang, Che-Yuan Che
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Patent number: 7622347Abstract: A method of forming a capacitor comprising the following steps. An inchoate capacitor is formed on a substrate within a capacitor area whereby portions of the substrate separate the inchoate capacitor from isolating shallow trench isolation (STI) structures. STIs. A first dielectric layer is formed over the structure. The first dielectric layer is patterned to: form a portion masking the inchoate capacitor; and expose at least portions of the STIs and the substrate portions separating the inchoate capacitor from the shallow trench isolation structures. Metal portions are formed at least over the substrate portions. A second dielectric layer is formed over the patterned first dielectric layer portion, the metal portions and the STIs, whereby the metal portions formed at least over the substrate portions prevent formation of native oxide on at least the substrate portions. The invention also includes the structures formed thereby.Type: GrantFiled: January 12, 2007Date of Patent: November 24, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Min-Hsiung Chiang, Chih-Ta Wu, Tsung-Hsun Huang
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Publication number: 20080116496Abstract: A novel SOC structure and method of making the same are provided. An SOC comprises a logic region, an SRRM and a DRAM region. The storage capacitor in a DRAM cell is formed in the first dielectric layer in an MIM (metal-insulator-metal) configuration, having a large vertical surface area. A butted contact, formed in said first dielectric layer, comprises a bottom portion abutting a first and second conductive region in an SRAM cell, and a vertically aligned top portion coupled to a first metal layer. The top portion has a substantially larger depth than that of the bottom portion, while substantially smaller in size. Forming this SOC structure does not require adding complex, error-prone additional processing steps on an existing CMOS manufacturing process, thus having little impact on the overall SOC product yield.Type: ApplicationFiled: June 1, 2007Publication date: May 22, 2008Inventors: Kuo-Chyuan Tzeng, Kuo-Chiang Ting, Chen-Jong Wang, Min-Hsiung Chiang, Chih-Yang Pai
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Patent number: 7332394Abstract: A method of integrating the fabrication of a capacitor cell and a logic device region, wherein the surface area of a capacitor region is increased, and the risk of a capacitor depletion phenomena is reduced, has been developed. After formation of insulator filled STI regions featuring tapered sides, a portion of the insulator layer in an STI region is recessed below the top surface of the semiconductor substrate exposing a bare, tapered side of the semiconductor substrate. Ion implantation into the tapered side of the portion of semiconductor substrate exposed in the recessed STI portion, as well as into a top portion of semiconductor substrate located adjacent to the recessed STI portion, results in formation of a capacitor region now greater in surface area than a counterpart capacitor region which is formed via implantation into only a top portion of semiconductor substrate.Type: GrantFiled: November 1, 2005Date of Patent: February 19, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Min-Hsiung Chiang
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Patent number: 7238566Abstract: A method of forming a one-transistor memory cell includes the steps of: forming a dielectric layer over a substrate having a pass-gate formed thereon; forming an opening in the dielectric layer to expose a portion of the substrate at least adjacent to the pass-gate; forming a capacitor dielectric layer on sidewalls of the opening in the dielectric layer and on the exposed portion of the substrate; and forming an electrode layer over the capacitor dielectric layer. A one-transistor memory cell is also disclosed. The one-transistor memory cell has a substrate having a pass-gate formed thereover. A dielectric layer is formed over the pass-gate and the substrate and has an opening exposing a portion of the substrate adjacent to the pass-gate. A capacitor dielectric layer is formed on sidewalls of the opening and on the exposed portion of the substrate. An electrode layer is formed on the capacitor dielectric layer.Type: GrantFiled: October 8, 2003Date of Patent: July 3, 2007Assignee: Taiwan Semiconductor Manufacturing CompanyInventor: Min-Hsiung Chiang
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Publication number: 20070111438Abstract: A method of forming a capacitor comprising the following steps. An inchoate capacitor is formed on a substrate within a capacitor area whereby portions of the substrate separate the inchoate capacitor from isolating shallow trench isolation (STI) structures. STIs. A first dielectric layer is formed over the structure. The first dielectric layer is patterned to: form a portion masking the inchoate capacitor; and expose at least portions of the STIs and the substrate portions separating the inchoate capacitor from the shallow trench isolation structures. Metal portions are formed at least over the substrate portions. A second dielectric layer is formed over the patterned first dielectric layer portion, the metal portions and the STIs, whereby the metal portions formed at least over the substrate portions prevent formation of native oxide on at least the substrate portions. The invention also includes the structures formed thereby.Type: ApplicationFiled: January 12, 2007Publication date: May 17, 2007Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Min-Hsiung Chiang, Chih-Ta Wu, Tsung-Hsun Huang
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Patent number: 7208369Abstract: Semiconductor devices having a dual polysilicon electrode and a method of manufacturing are provided. The semiconductor devices include a first polysilicon layer deposited on a second polysilicon layer. Each polysilicon layer may be doped individually. The method also allows for some semiconductor devices on a wafer to have a single polysilicon wafer and other devices to have a dual polysilicon layer. In one embodiment, the semiconductor devices are utilized to form a memory device wherein the storage capacitors and transistors located in the cell region are formed with a dual polysilicon layer and devices in the periphery region are formed with a single polysilicon layer.Type: GrantFiled: September 15, 2003Date of Patent: April 24, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Yang Pai, Min-Hsiung Chiang, Chen-Jong Wang, Shou-Gwo Wuu
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Patent number: 7180116Abstract: A method of forming a capacitor comprising the following steps. An inchoate capacitor is formed on a substrate within a capacitor area whereby portions of the substrate separate the inchoate capacitor from isolating shallow trench isolation (STI) structures. STIs. A first dielectric layer is formed over the structure. The first dielectric layer is patterned to: form a portion masking the inchoate capacitor; and expose at least portions of the STIs and the substrate portions separating the inchoate capacitor from the shallow trench isolation structures. Metal portions are formed at least over the substrate portions. A second dielectric layer is formed over the patterned first dielectric layer portion, the metal portions and the STIs, whereby the metal portions formed at least over the substrate portions prevent formation of native oxide on at least the substrate portions. The invention also includes the structures formed thereby.Type: GrantFiled: June 4, 2004Date of Patent: February 20, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Min-Hsiung Chiang, Chih-Ta Wu, Tsung-Hsun Huang
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Publication number: 20060057803Abstract: A method of integrating the fabrication of a capacitor cell and a logic device region, wherein the surface area of a capacitor region is increased, and the risk of a capacitor depletion phenomena is reduced, has been developed. After formation of insulator filled STI regions featuring tapered sides, a portion of the insulator layer in an STI region is recessed below the top surface of the semiconductor substrate exposing a bare, tapered side of the semiconductor substrate. Ion implantation into the tapered side of the portion of semiconductor substrate exposed in the recessed STI portion, as well as into a top portion of semiconductor substrate located adjacent to the recessed STI portion, results in formation of a capacitor region now greater in surface area than a counterpart capacitor region which is formed via implantation into only a top portion of semiconductor substrate.Type: ApplicationFiled: November 1, 2005Publication date: March 16, 2006Inventor: Min-Hsiung Chiang