Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to self-aligned back-plane and well contacts for a fully depleted silicon on insulator device and methods of manufacture. The structure includes a back-plane, a p-well and an n-well formed within a bulk substrate; a contact extending from each of the back-plane, the p-well and the n-well; a gate structure formed above the back-plane, the p-well and the n-well; and an insulating spacer isolating the contact of the back-plane from the gate structure.

Abstract: A finFET includes a source or a drain including: a first semiconductor fin extending parallel to a second semiconductor fin, and a semiconductor connector fin creating a first semiconductor fin loop by connecting an end of the first semiconductor fin to an end of the second semiconductor fin. A diffusion break isolates the source or the drain, and is positioned about the first semiconductor connector fin and the ends of the first semiconductor fin and the second semiconductor fin. The semiconductor connector fin provides an epitaxial growth surface adjacent the diffusion break. A related method and IC structure are also disclosed.

Abstract: Methods for forming an efficient and effective crossed-fins FinFET device for sensing and measuring magnetic fields and resulting devices are disclosed. Embodiments include forming first-fins, parallel to and spaced from each other, in a first direction on a substrate; forming second-fins, parallel to and spaced from each other on the substrate, in a same plane as the first fins and in a second direction perpendicular to and crossing the first-fins; forming a dummy gate with a spacer on each side over channel areas of the first and second fins; forming source/drain (S/D) regions at opposite ends of each first and second fin; forming an ILD over the fins and the dummy gate and planarizing to reveal the dummy gate; removing the dummy gate, forming a cavity; and forming a high-k/metal gate in the cavity.

Abstract: A flash memory device and its manufacturing method are presented. The flash memory device includes a substrate; a memory unit on the substrate, comprising a channel structure, wherein the channel structure comprises, sequentially from inner to outer of the channel structure, a channel layer comprising a first component substantially perpendicular to an upper surface of the substrate and a second component on the first component, a tunnel insulation layer wrapped around the channel layer, a charge capture layer wrapped around the tunnel insulation layer, and a blocking layer wrapped around the charge capture layer; a plurality of gate structures wrapped around the channel structure and arranged along a symmetry axis of the channel structure with a topmost gate structure wrapped around the second component; and a channel contact component connecting to, and forming a Schottky contact with, the second component of the channel layer. This device reduces the leakage current.

Abstract: A flash memory device includes a substrate, an electrode layer on a portion of the substrate, the electrode layer being a work function adjusting layer or a metal silicide layer, and a memory cell. The memory cell includes a channel structure on the electrode layer and having, from the inside to the outside in this order, a channel layer in contact with the electrode layer, a tunneling insulator layer surrounding the channel layer, a charge trapping layer surrounding the tunneling insulator layer, and a barrier layer surrounding the charge trapping layer, and a plurality of gate structures surrounding the channel structure along an axial direction of the channel structure. The flash memory device may be formed on a dielectric layer, and its fabrication process is thus compatible with back end of line processes.

Abstract: At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.

Abstract: A method of reducing parasitic capacitance includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with fin(s) thereon, the fin(s) having at least two dummy transistors integrated therewith and separated by a dielectric region, the dummy transistors including dummy gates with spacers and gate caps, the fin(s) having ends tucked by the dummy gates. The method further includes removing the dummy gates and gate caps, resulting in gate trenches, protecting area(s) of the structure during fabrication process(es) where source/drain parasitic capacitance may occur, and forming air-gaps at a bottom portion of unprotected gate trenches to reduce parasitic capacitance.

Abstract: FinFET structures and methods of forming such structures. The FinFET structures including a substrate; at least two gates disposed on the substrate; a plurality of source/drain regions within the substrate adjacent to each of the gates; a dielectric disposed between each gate and the plurality of source/drain regions adjacent to each gate; a dielectric capping layer disposed on a first one of the at least two gates, wherein no dielectric capping layer is disposed on a second one of the at least two gates; and a local interconnect electrically connected to the second one of the at least two gates, wherein the dielectric capping layer disposed on the first one of the at least two gates prevents an electrical connection between the local interconnect and the first one of the at least two gates.

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate structure between a pair of gate spacers within a dielectric layer and substantially surrounding a fin, wherein the gate structure is disposed adjacent to a channel region within the fin; and a source/drain contact extending within the dielectric layer to a source/drain region within a fin, the source/drain contact being separated from the gate structure by at least one gate spacer in the pair of gate spacers, wherein the channel region and the source/drain region provide electrical connection between the gate structure and the source/drain contact.

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices for forming conductive paths between fins for contact-to-gate shorting. One method includes, for instance: obtaining wafer with a substrate, at least one fin, at least one hard mask, and an oxide layer; etching the oxide layer to reveal at least one of a portion of the hard masks; forming sacrificial pillars over the substrate; forming sacrificial gates, wherein at least one sacrificial gate contacts at least one sacrificial pillar; growing an epitaxial layer between the at least one sacrificial gate and the at least one sacrificial pillar; starting a RMG process on the sacrificial gates; etching to remove the sacrificial pillars and form pillar openings; and completing the RMG process to fill the pillar openings and the gate openings with a metal.

Abstract: Disclosed are methods for stress memorization techniques. In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate including a channel region underlying, at least partially, the gate structure, the fabricating including: forming a source and drain cavity in the substrate; with an in situ doped semiconductor material, epitaxially growing a source and drain region within the source and drain cavity; performing an amorphization ion implantation process by implanting an amorphization ion material into the source and drain region; forming a capping material layer above the NMOS transistor device; with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the source and drain region; and removing the capping material layer.

Abstract: A semiconductor structure includes a semiconductor substrate, at least one first elongated region of n-type or p-type, and at least one other second elongated region of the other of n-type or p-type, the first and second elongated regions crossing such that the first elongated region and the second elongated region intersect at a common area, and a shared gate structure over each common area.

Abstract: Programmable via devices and fabrication methods thereof are presented. The programmable via devices include, for instance, a first metal layer and a second metal layer electrically connected by a via link. The via link includes a semiconductor portion and a metal portion, where the via link facilitates programming of the programmable via device by applying a programming current through the via link to migrate materials between the semiconductor portion and the metal portion to facilitate a change of an electrical resistance of the via link. In one embodiment, the programming current facilitates formation of at least one gap region within the via link, the at least one gap region facilitating the change of the electrical resistance of the via link.

Abstract: Capacitor structures having first electrodes at least partially embedded within a second electrode, and fabrication methods are presented. The methods include, for instance: providing the first electrodes at least partially within an insulator layer, the first electrodes comprising exposed portions; covering exposed portions of the first electrodes with a dielectric material; and forming the second electrode at least partially around the dielectric covered portions of the first electrodes, the second electrode being physically separated from the first electrodes by the dielectric material. In one embodiment, a method further includes exposing further portions of the first electrodes; and providing a contact structure in electrical contact with the further exposed portions of the first electrodes.

Abstract: A semiconductor structure includes a semiconductor substrate, at least one first elongated region of n-type or p-type, and at least one other second elongated region of the other of n-type or p-type, the first and second elongated regions crossing such that the first elongated region and the second elongated region intersect at a common area, and a shared gate structure over each common area.

Abstract: Methods for forming an efficient and effective crossed-fins FinFET device for sensing and measuring magnetic fields and resulting devices are disclosed. Embodiments include forming first-fins, parallel to and spaced from each other, in a first direction on a substrate; forming second-fins, parallel to and spaced from each other on the substrate, in a same plane as the first fins and in a second direction perpendicular to and crossing the first-fins; forming a dummy gate with a spacer on each side over channel areas of the first and second fins; forming source/drain (S/D) regions at opposite ends of each first and second fin; forming an ILD over the fins and the dummy gate and planarizing to reveal the dummy gate; removing the dummy gate, forming a cavity; and forming a high-k/metal gate in the cavity.

Abstract: Diodes and fabrication methods thereof are presented. The diodes include, for instance: a first semiconductor region disposed at least partially within a substrate, the first semiconductor region having a first conductivity type; and a second semiconductor region disposed at least partially within the first semiconductor region, the second semiconductor region having a second conductivity type, wherein the first semiconductor region separates the second semiconductor region from the substrate. In one embodiment, the substrate and the first semiconductor region have U-shaped boundary. In a further embodiment, the first semiconductor region comprises an alloy of a first material and a second material, where the concentration of the second material varies from a maximum to a minimum, where the first semiconductor region adjacent to the second semiconductor region has the minimum of the concentration of the second material.

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate structure between a pair of gate spacers within a dielectric layer and substantially surrounding a fin, wherein the gate structure is disposed adjacent to a channel region within the fin; and a source/drain contact extending within the dielectric layer to a source/drain region within a fin, the source/drain contact being separated from the gate structure by at least one gate spacer in the pair of gate spacers, wherein the channel region and the source/drain region provide electrical connection between the gate structure and the source/drain contact.

Abstract: Fin field effect transistors (FinFETs) include air-gaps between adjacent metal contacts and/or between metal contacts and the transistor gate. The air-gaps are formed during non-conformal deposition of an isolation dielectric in conjunction with a metal-first process to form the conductive structures.

Abstract: Methods, apparatus, and systems for fabricating and using a semiconductor device comprising a first conductive element; a second conductive element; and an e-fuse comprising a first region comprising a conductive oxide of a first metal; and a second region comprising a second metal, wherein an oxide of the second metal is resistive; wherein the e-fuse is electrically connected to both the first conductive element and the second conductive element.