Patents by Inventor Min Hyo Park
Min Hyo Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11980610Abstract: Disclosed are an oral solid dosage form composition comprising an active ingredient and a solubilizing carrier wherein a foaming ingredient is used to improve disintegration, dispersion or dissolution, and a preparation method therefor.Type: GrantFiled: October 30, 2018Date of Patent: May 14, 2024Assignee: SAMYANG HOLDINGS CORPORATIONInventors: Sang Yeob Park, Hye Jung Lim, Jae Young Lee, Min Hyo Seo, Sa Won Lee
-
Patent number: 11984559Abstract: A systems and methods for tracking a position of an electrode. The system may include: a notching controller configured to store pitch information of a unit electrode and to acquire electrode coordinate information of the electrode in a roll-to-roll state during a notching process and a cell identification (ID) of the unit electrode; a calculator configured to calculate coordinates of the cell ID from the pitch information and the cell ID; a roll map generator configured to generate a roll map based on the electrode coordinate information transmitted from the notching controller; and a mapping part configured to compare the coordinates of the roll map with the coordinates of the cell ID to derive an electrode position of the electrode during the electrode manufacturing process from which the unit electrode originates.Type: GrantFiled: August 8, 2022Date of Patent: May 14, 2024Assignee: LG ENERGY SOLUTION, LTD.Inventors: Jae Hwan Lee, Jong Seok Park, Dong Yeop Lee, Jun Hyo Su, Ki Deok Han, Byoung Eun Han, Seung Huh, Su Wan Park, Gi Yeong Jeon, Min Su Kim
-
Publication number: 20240151524Abstract: An apparatus for generating a roll map of a merge-wound electrode includes a position measurement device configured to acquire coordinate value data for a longitudinal position of an electrode according to an amount of rotation of the rewinder. The apparatus includes an input device configured to input an input signal indicating a start of merge-winding or an end of merge-winding, a seam detector configured to detect a seam, a reference point detector configured to detect a plurality of reference points of the merge-wound electrode, and a roll map generator configured to generate a roll map for simulating the merge-wound electrode moving in a roll-to-roll state based on the input signal of the input device, and to display the longitudinal coordinate values of the electrode, the electrode coordinate values of the seam, and the electrode coordinate values of the plurality of reference points of the merge-wound electrode on the roll map.Type: ApplicationFiled: November 7, 2022Publication date: May 9, 2024Inventors: Dong Yeop LEE, Jong Seok PARK, Jun Hyo SU, Ki Deok HAN, Byoung Eun HAN, Seung HUH, Su Wan PARK, Gi Yeong JEON, Jae Hwan LEE, Min Su KIM
-
Publication number: 20240141673Abstract: The present invention relates to a multi-functional support pole assembly. In particular, the present invention provides the advantage of improving operational reliability as well as preventing deterioration of urban area appearance, by comprising: a pole body provided in a hollow form and having a plurality of antenna mounting grooves formed through cutting so as to be spaced apart at a predetermined angle in a circumferential direction such that a plurality of antenna devices can be installed in the circumferential direction; and ventilation panels which are attached to remaining portions of the antenna mounting grooves not occupied by the plurality of antenna devices, and have a plurality of ventilation holes for introducing external air into the interior of the pole body.Type: ApplicationFiled: January 6, 2024Publication date: May 2, 2024Applicant: KMW INC.Inventors: Duk Yong KIM, In Ho KIM, Sang Hyo KANG, Kyo Sung JI, Chi Back RYU, Min Sik PARK, Hee KIM
-
Publication number: 20240128630Abstract: The present invention relates to a support pole assembly for mounting an antenna and, particularly, to a support pole assembly for mounting an antenna, comprising: a support pole which is formed in a hollow structure and has an antenna device mounting hole formed at the circumferential surface thereof; an antenna device which is mounted to the support pole while passing through and covering the antenna device mounting hole and the rear portion of which is placed in the inner space of the support pole. Accordingly, the present invention provides an advantage in that the protrusion amount of the antenna device with respect to the support pole is reduced and thus the space required for mounting the antenna device can be reduced.Type: ApplicationFiled: December 28, 2023Publication date: April 18, 2024Applicant: KMW INC.Inventors: Duk Yong KIM, Chi Back RYU, Min Sik PARK, Kyo Sung JI, In Ho KIM, Sang Hyo KANG, Min Soo KIM, Hee KIM, Young Ji HONG
-
Publication number: 20240127722Abstract: A wireless communication device support assembly is disclosed, including a support pole comprising a hollow interior, a first frame having a polygonal shape disposed on top of the support pole, a plurality of wireless communication devices disposed inside the first frame, at least one or more rotational advertising apparatuses controllably elevated in a direction parallel to a longitudinal direction of the support pole, a drive unit configured to elevate or lower the rotational advertising apparatus, and a plurality of lift ropes having first ends connected with tops of the rotational advertising apparatuses and second ends connected with the drive unit.Type: ApplicationFiled: December 25, 2023Publication date: April 18, 2024Applicant: KMW INC.Inventors: Duk Yong KIM, Chi Back RYU, Min Sik PARK, Kyo Sung JI, In Ho KIM, Sang Hyo KANG, Min Soo KIM, Hee KIM
-
Publication number: 20240097218Abstract: Methods and systems for executing tracking and monitoring manufacturing data of a battery are disclosed. One method includes: receiving, by a server system, sensing data of the battery from a sensing system; generating, by the server system, mapping data based on the sensing data; generating, by the server system, identification data of the battery based on the sensing data; generating, by the server system, monitoring data of the battery based on the sensing data, the identification data, and the mapping data; and generating, by the server system, display data for displaying a simulated electrode of the battery on a graphical user interface based on the monitoring data of the battery.Type: ApplicationFiled: August 31, 2023Publication date: March 21, 2024Inventors: Min Kyu Sim, Jong Seok Park, Min Su Kim, Jae Hwan Lee, Ki Deok Han, Eun Ji Jo, Su Wan Park, Gi Yeong Jeon, June Hee Kim, Wi Dae Park, Dong Min Seo, Seol Hee Kim, Dong Yeop Lee, Jun Hyo Su, Byoung Eun Han, Seung Huh
-
Publication number: 20240092974Abstract: The present disclosure relates to a polyimide-based resin film comprising a polyimide-based resin containing a polyimide repeating unit represented by Chemical Formula 1 and a polyimide repeating unit represented by Chemical Formula 2, a substrate for display device, and an optical device using the same.Type: ApplicationFiled: September 14, 2022Publication date: March 21, 2024Applicant: LG CHEM, LTD.Inventors: Mi Eun KANG, Chan Hyo PARK, Jinyoung PARK, Chae Won PARK, Min Wook LEE
-
Patent number: 8168475Abstract: Provided are a semiconductor package which is small in size but includes a large number of terminals disposed at intervals equal to or greater than a minimum pitch, and a method of fabricating the semiconductor package. The semiconductor package includes a semiconductor chip having a bottom surface on which a plurality of bumps are formed, redistribution layer patterns formed under the semiconductor chip and each including a first part electrically connected to at least one of the bumps and a second part electrically connected to the first part, an encapsulation layer surrounding at least a top surface of the semiconductor chip, and a patterned insulating layer formed below the redistribution layer patterns and exposing at least parts of the second parts of the redistribution layer patterns.Type: GrantFiled: April 15, 2010Date of Patent: May 1, 2012Assignee: Fairchild Korea Semiconductor, Ltd.Inventors: Seung-yong Choi, Min-hyo Park
-
Patent number: 7936054Abstract: A semiconductor package is disclosed. Particularly, a multi-chip package is disclosed, which can stably maintain insulation between a plurality of semiconductor chips and effectively release heat to the outside. The semiconductor package includes an insulation layer including a diamond layer formed by a chemical vapor deposition method between a lead frame or a heat sink and the semiconductor chips disposed thereon.Type: GrantFiled: December 10, 2008Date of Patent: May 3, 2011Assignee: Fairchild Korea Semiconductor Ltd.Inventors: Joo-yang Eom, Min-hyo Park, Seung-yong Choi
-
Publication number: 20100203684Abstract: Provided are a semiconductor package which is small in size but includes a large number of terminals disposed at intervals equal to or greater than a minimum pitch, and a method of fabricating the semiconductor package. The semiconductor package includes a semiconductor chip having a bottom surface on which a plurality of bumps are formed, redistribution layer patterns formed under the semiconductor chip and each including a first part electrically connected to at least one of the bumps and a second part electrically connected to the first part, an encapsulation layer surrounding at least a top surface of the semiconductor chip, and a patterned insulating layer formed below the redistribution layer patterns and exposing at least parts of the second parts of the redistribution layer patterns.Type: ApplicationFiled: April 15, 2010Publication date: August 12, 2010Applicant: Fairchild Korea Semiconductor Ltd.Inventors: Seung-yong Choi, Min-hyo Park
-
Patent number: 7728437Abstract: Provided are a semiconductor package which is small in size but includes a large number of terminals disposed at intervals equal to or greater than a minimum pitch, and a method of fabricating the semiconductor package. The semiconductor package includes a semiconductor chip having a bottom surface on which a plurality of bumps are formed, redistribution layer patterns formed under the semiconductor chip and each including a first part electrically connected to at least one of the bumps and a second part electrically connected to the first part, an encapsulation layer surrounding at least a top surface of the semiconductor chip, and a patterned insulating layer formed below the redistribution layer patterns and exposing at least parts of the second parts of the redistribution layer patterns.Type: GrantFiled: November 23, 2005Date of Patent: June 1, 2010Assignee: Fairchild Korea Semiconductor, Ltd.Inventors: Soung-yong Choi, Min-hyo Park
-
Patent number: 7632719Abstract: A packaged semiconductor device (a wafer-level chip scale package) containing a conductive adhesive material as an electrical interconnect route between the semiconductor die and a patterned conductive substrate is described. The patterned conductive substrate acts not only as a substrate, but also as a redistribution layer that converts the dense pad layout of the die to a larger array configuration of the solder balls in the circuit board. Using the invention allows the formation of a lower priced chip scale package that also overcomes the restriction of the die size used in die-sized chip packages and the input-output pattern that can be required by the printed circuit board. Thus, the invention can provide a familiar pitch (i.e., interface) to the printed circuit board for any small die.Type: GrantFiled: January 7, 2009Date of Patent: December 15, 2009Assignee: Fairchild Korea Semiconductor, LtdInventors: Seung Yong Choi, Min Hyo Park, Ji Hwan Kim, Rajeev Joshi
-
Publication number: 20090189272Abstract: Provided are wafer level chip scale packages, each having a redistribution substrate in which a pad pitch is improved, and methods of fabricating the same. An exemplary wafer level chip scale package includes a semiconductor chip and a redistribution substrate. The semiconductor chip includes a plurality of pads arranged with a first pitch on a first surface thereof. The redistribution substrate includes a plurality of connection wires arranged with a second pitch, which is greater than the first pitch, on a first surface thereof. The redistribution substrate expands a pad pitch from the first pitch to the second pitch by electrically connecting the pads to the connection wires.Type: ApplicationFiled: January 21, 2009Publication date: July 30, 2009Inventors: Min-hyo Park, Seung-yong Choi
-
Publication number: 20090174044Abstract: A semiconductor package is disclosed. Particularly, a multi-chip package is disclosed, which can stably maintain insulation between a plurality of semiconductor chips and effectively release heat to the outside. The semiconductor package includes an insulation layer including a diamond layer formed by a chemical vapor deposition method between a lead frame or a heat sink and the semiconductor chips disposed thereon.Type: ApplicationFiled: December 10, 2008Publication date: July 9, 2009Inventors: Joo-yang Eom, Min-hyo Park, Seung-yong Choi
-
Publication number: 20070114661Abstract: Provided are a semiconductor package which is small in size but includes a large number of terminals disposed at intervals equal to or greater than a minimum pitch, and a method of fabricating the semiconductor package. The semiconductor package includes a semiconductor chip having a bottom surface on which a plurality of bumps are formed, redistribution layer patterns formed under the semiconductor chip and each including a first part electrically connected to at least one of the bumps and a second part electrically connected to the first part, an encapsulation layer surrounding at least a top surface of the semiconductor chip, and a patterned insulating layer formed below the redistribution layer patterns and exposing at least parts of the second parts of the redistribution layer patterns.Type: ApplicationFiled: November 23, 2005Publication date: May 24, 2007Inventors: Soung-yong Choi, Min-hyo Park