Patents by Inventor Min-Lu Kao

Min-Lu Kao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145575
    Abstract: A semiconductor device includes a substrate, a channel layer, a first barrier layer, a source/drain contact, and a gate layer. The channel layer is on the substrate. The first barrier layer is on the channel layer and the thickness of the first barrier layer is less than 6 nm. The source/drain contact is on the first barrier layer and is directly contact with the first barrier layer. The gate layer is over the first barrier layer.
    Type: Application
    Filed: May 3, 2023
    Publication date: May 2, 2024
    Inventors: Edward Yi CHANG, You-Chen WENG, Min-Lu KAO
  • Publication number: 20240136432
    Abstract: A high electron mobility transistor includes a growth substrate, a lattice matching layer, an back-barrier layer, an electron blocking layer, a channel layer, an active layer, a source, a gate, and a drain. The lattice matching layer and the back-barrier layer are formed on the growth substrate. The back-barrier layer includes GaN doped with C. The electron blocking layer is formed on the back-barrier layer. The electron blocking layer includes AlGaN, wherein the doping percent of Al atoms of the AlGaN is 3˜5% and the doping percent of Ga atoms of the AlGaN is 95˜97%. The electron blocking layer has a thickness of 2˜5 nm. The channel layer and the active layer are formed on the electron blocking layer. The source, the gate, and the drain are formed on the active layer.
    Type: Application
    Filed: January 13, 2023
    Publication date: April 25, 2024
    Applicants: National Yang Ming Chiao Tung University, National Chung-Shan Institute of Science and Technology
    Inventors: Edward Yi CHANG, You-Chen WENG, Min-Lu KAO
  • Publication number: 20240136422
    Abstract: A high electron mobility transistor and a method for fabricating the same is disclosed. Firstly, a lattice matching layer, a channel layer, and an AlGaN layer are sequentially formed on a growth substrate. The AlGaN layer includes a first area, a second area, and a third area, wherein the second area is located between the first area and the third area. Then, an insulation block is formed on the second area of the AlGaN layer and two GaN blocks are respectively formed on the first area and the third area of the AlGaN layer. Two InAlGaN blocks are respectively formed on the GaN blocks and the insulation block is removed. Finally, a gate is formed to interfere the second area of the AlGaN layer and a source and a drain are respectively formed on the InAlGaN blocks.
    Type: Application
    Filed: January 13, 2023
    Publication date: April 25, 2024
    Applicants: National Yang Ming Chiao Tung University, National Chung-Shan Institute of Science and Technology
    Inventors: Edward Yi CHANG, You-Chen WENG, Min-Lu Kao