Patents by Inventor Min-ok NA
Min-ok NA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10950521Abstract: Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.Type: GrantFiled: September 10, 2019Date of Patent: March 16, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min-Ok Na, Jongkook Kim, Hyo-Chang Ryu, Jin-woo Park, BongJin Son, Jangwoo Lee
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Patent number: 10593652Abstract: An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.Type: GrantFiled: June 21, 2019Date of Patent: March 17, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Heung-Kyu Kwon, Min-Ok Na, Sung-Woo Park, Ji-Hyun Park, Su-Min Park
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Publication number: 20200006188Abstract: Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.Type: ApplicationFiled: September 10, 2019Publication date: January 2, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Min-Ok Na, Jongkook Kim, Hyo-Chang Ryu, Jin-woo Park, BongJin Son, Jangwoo Lee
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Publication number: 20190319012Abstract: An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.Type: ApplicationFiled: June 21, 2019Publication date: October 17, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Heung-Kyu KWON, Min-Ok NA, Sung-Woo Park, Ji-Hyun Park, Su-Min Park
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Patent number: 10431522Abstract: Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.Type: GrantFiled: December 28, 2017Date of Patent: October 1, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Ok Na, Jongkook Kim, Hyo-Chang Ryu, Jin-woo Park, BongJin Son, Jangwoo Lee
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Patent number: 10403606Abstract: A method for fabricating a semiconductor package including mounting a first semiconductor chip on a first substrate, disposing a first connector on the first substrate, placing a molding control film on the first semiconductor chip to horizontally extend over the first substrate, filling a space between the molding control film and the first substrate with a molding compound such that the molding compound contacts side surfaces of the first semiconductor chip and covers the first connector and does not cover a top surface of the first semiconductor chip, detaching the molding control film, forming an opening through the molding compound to expose a portion of the first connector, disposing a second connector and a second semiconductor chip on opposite surfaces of a second substrate, respectively, and placing the second substrate on the first substrate such that the second connector contacts the first connector may be provided.Type: GrantFiled: May 4, 2018Date of Patent: September 3, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Heung-Kyu Kwon, Min-Ok Na, Sung-Woo Park, Ji-Hyun Park, Su-Min Park
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Publication number: 20180331071Abstract: An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.Type: ApplicationFiled: May 4, 2018Publication date: November 15, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Heung-Kyu KWON, Min-Ok NA, Sung-Woo PARK, Ji-Hyun PARK, Su-Min PARK
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Publication number: 20180145006Abstract: Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.Type: ApplicationFiled: December 28, 2017Publication date: May 24, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Min-Ok NA, Jongkook Kim, Hyo-Chang Ryu, Jin-woo Park, BongJin Son, Jangwoo Lee
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Patent number: 9978721Abstract: An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.Type: GrantFiled: August 19, 2016Date of Patent: May 22, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Heung-Kyu Kwon, Min-Ok Na, Sung-Woo Park, Ji-Hyun Park, Su-Min Park
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Patent number: 9899294Abstract: Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.Type: GrantFiled: August 12, 2013Date of Patent: February 20, 2018Assignee: Samsung Electronics co., Ltd.Inventors: Min-Ok Na, Jongkook Kim, Hyo-Chang Ryu, Jin-woo Park, BongJin Son, Jangwoo Lee
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Publication number: 20160358893Abstract: An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.Type: ApplicationFiled: August 19, 2016Publication date: December 8, 2016Applicant: Samsung Electronics Co., Ltd.Inventors: Heung-Kyu KWON, Min-Ok NA, Sung-Woo PARK, Ji-Hyun PARK, Su-Min PARK
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Publication number: 20160190035Abstract: Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.Type: ApplicationFiled: August 12, 2013Publication date: June 30, 2016Inventors: Min-Ok NA, JongKook KIM, Hyo-Chang RYU, Jin-woo PARK, BongJin SON, Jang Woo LEE
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Patent number: 9214484Abstract: An image sensor package may include: a package substrate including a chip attachment area on an upper surface thereof, a pad area having a plurality of pads around the chip attachment area, and a holder attachment area at an outside of the pad area, wherein an upper surface of the holder attachment area is at a lower level than an upper surface of the pad area; an image sensor chip mounted on the chip attachment area of the package substrate; a transparent member above the package substrate and configured to cover the image sensor chip; and a holder on the holder attachment area of the package substrate and configured to fix the transparent member.Type: GrantFiled: August 4, 2014Date of Patent: December 15, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Ok-Gyeong Park, Min-Ok Na
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STACKED SEMICONDUCTOR PACKAGES, METHODS FOR FABRICATING THE SAME, AND /OR SYSTEMS EMPLOYING THE SAME
Publication number: 20150228627Abstract: An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.Type: ApplicationFiled: April 22, 2015Publication date: August 13, 2015Inventors: Heung-Kyu KWON, Min-Ok NA, Sungwoo PARK, Ji-hyun PARK, Su-min PARK -
Patent number: 9042115Abstract: An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.Type: GrantFiled: July 3, 2013Date of Patent: May 26, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Heung-Kyu Kwon, Min-Ok Na, Sung-Woo Park, Ji-Hyun Park, Su-Min Park
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Patent number: 9040351Abstract: A stack package includes a lower package including a lower package substrate and a lower semiconductor chip disposed on the lower package substrate, an upper package including an upper package substrate and an upper semiconductor chip disposed on the upper package substrate, a fastening element formed between a top surface of the lower semiconductor chip and a bottom surface of the upper package substrate, and a halogen-free inter-package connector connecting the lower package substrate to the upper package substrate.Type: GrantFiled: July 24, 2014Date of Patent: May 26, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Heung-Kyu Kwon, Jae-Wook Yoo, Hyon-Chol Kim, Su-Chang Lee, Min-Ok Na
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Publication number: 20150130011Abstract: An image sensor package may include: a package substrate including a chip attachment area on an upper surface thereof, a pad area having a plurality of pads around the chip attachment area, and a holder attachment area at an outside of the pad area, wherein an upper surface of the holder attachment area is at a lower level than an upper surface of the pad area; an image sensor chip mounted on the chip attachment area of the package substrate; a transparent member above the package substrate and configured to cover the image sensor chip; and a holder on the holder attachment area of the package substrate and configured to fix the transparent member.Type: ApplicationFiled: August 4, 2014Publication date: May 14, 2015Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ok-Gyeong PARK, Min-Ok NA
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Publication number: 20140335657Abstract: A stack package includes a lower package including a lower package substrate and a lower semiconductor chip disposed on the lower package substrate, an upper package including an upper package substrate and an upper semiconductor chip disposed on the upper package substrate, a fastening element formed between a top surface of the lower semiconductor chip and a bottom surface of the upper package substrate, and a halogen-free inter-package connector connecting the lower package substrate to the upper package substrate.Type: ApplicationFiled: July 24, 2014Publication date: November 13, 2014Applicant: Samsung Electronics Co., LtdInventors: HEUNG-KYU KWON, JAE-WOOK YOO, HYON-CHOL KIM, SU-CHANG LEE, MIN-OK NA
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Patent number: 8829686Abstract: A package-on-package assembly includes first and second packages and an adhesion member positioned between the first and second packages and adhering the first and second packages to one another. The first package may include a first substrate having a first surface and a second surface facing each other and including a land pad formed on the first surface, a first semiconductor chip formed on the first surface, and a first encapsulant member encapsulating the first surface and the first semiconductor chip and including a through-via spaced apart from the first semiconductor chip and exposing the land pad and a trench formed between the first semiconductor chip and the through-via, and wherein at least a portion of the trench is filled with adhesion member material.Type: GrantFiled: November 15, 2012Date of Patent: September 9, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Sun Hong, Young-Min Kim, Jung-Woo Kim, Min-Ok Na, Hyo-Chang Ryu, Jong-Bo Shim
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Patent number: 8709879Abstract: A semiconductor package includes a substrate having an insulation layer. The insulation layer has a first region having a first surface roughness and a second region having a second surface roughness. A semiconductor chip is mounted in the first region, and an underfill resin solution is filled into the space between the semiconductor chip and the insulation layer. The roughness of the second region prevents the underfill resin from flowing out from the semiconductor chip to thereby reduce a size of the semiconductor package.Type: GrantFiled: March 15, 2013Date of Patent: April 29, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-hyun Park, Heungkyu Kwon, Min-Ok Na, Taehwan Kim