Abstract: A low level contact resistance (LLCR) testing apparatus comprises a test board, an interface board, and a patch board. The test board comprises a processor socket. The interface board connects to both the test board and the patch board. The patch board connects to a contact resistance tester. An LLCR system comprising the LLCR testing apparatus and a contact resistance tester can be portable. The test board can accommodate thermal management solutions of varying sizes and types. Different test board designs can accommodate different socket-processor configurations and the different test boards can be easily accommodated by an LLCR testing apparatus due to its modular design.

Abstract: Warpage reduction through laminate glass cloth design modification is described herein. In one example, a substrate for a microelectronic assembly, includes one or more glass-cloth containing layers. At least one of the glass-cloth containing layers includes a glass cloth having a weave including: a first plurality of parallel glass fibers, a second plurality of parallel glass fibers, and a third plurality of parallel glass fibers interwoven with one another in a plane. The second plurality of parallel glass fibers crosses the first plurality of glass fibers at a first angle, and the third plurality of parallel glass fibers crosses the first plurality of glass fibers at a second angle and crosses the second plurality of glass fibers at a third angle. In one example, the glass cloth weave includes a hexagonal pattern.

Abstract: Methods, apparatus, systems, and articles of manufacture to improve pin contact are disclosed. An apparatus disclosed herein includes a back plate, a circuit board disposed between the back plate and a socket, and a spring sheet disposed between the back plate and the circuit board.

Abstract: Devices and methods are shown that use sensors to detect physical characteristics of an IC circuit or other device over time. The physical characteristics and time data may be used to calculate a damage metric of the IC circuit or other device. The damage metric may be used to notify a user about a condition of the IC circuit or other device.

Abstract: Attachment structures for electrically coupling a microelectronic package to a microelectronic board/interposer including joint pads formed on the microelectronic board/interposer which provide a gap between respective openings in a solder resist layer of the microelectronic substrate and each of the joint pads. Such attachment structures may reduce or substantially eliminate contact between a solder interconnect and a solder resist layer of the microelectronic board/interposer, which may, in turn, reduce or substantially eliminate the potential of crack initiation and propagation at contact areas between the solder interconnect and a solder resist layer of the microelectronic board/interposer due to stresses induced by a mismatch of thermal expansion between the microelectronic package and the microelectronic board/interposer during thermal cycling.