Patents by Inventor Min-San Huang
Min-San Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190263173Abstract: A graphical heat transfer printing structure contains: a flexible layer, an adhesion layer, and a fluff layer. The flexible layer is made of flexible materials, and the adhesion layer is made of adhesive flexible material and covers on a top of the flexible layer. Furthermore, the fluff layer is defined between the flexible layer and the adhesion layer, and the fluff layer includes multiple fluffs flocked on the flexible layer and into the adhesion layer.Type: ApplicationFiled: September 20, 2016Publication date: August 29, 2019Inventors: Min San Huang, Chia Rong Liu
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Patent number: 8486509Abstract: A pattern having variable colors can be attached on a soft material of wearing apparels or household cloths. The pattern is constituted of decorative blocks provided on the surface of the cloth or the soft material and a plurality of color-shielding pieces embedded on the surface of the decorative blocks. At least two opposite outer sides of the color-shielding piece are respectively provided with a colored block, so that the decorative blocks represent a visual effect of variable colors when viewed from different angles since the color-shielding pieces shield the colored blocks.Type: GrantFiled: August 21, 2006Date of Patent: July 16, 2013Inventor: Min-San Huang
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Patent number: 7803692Abstract: A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.Type: GrantFiled: September 18, 2009Date of Patent: September 28, 2010Assignee: Powerchip Semiconductor Corp.Inventors: Min-San Huang, Hann-Jye Hsu, Yung-Chung Yao
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Publication number: 20100003796Abstract: A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.Type: ApplicationFiled: September 18, 2009Publication date: January 7, 2010Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Min-San Huang, Hann-Jye Hsu, Yung-Chung Yao
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Patent number: 7612433Abstract: A method of manufacturing semiconductor devices having self-aligned contacts is provided. Multiple isolation structures are formed on the substrate to define an active area. Multiple gate structures are formed on the substrate. Multiple doped areas are formed in the substrate beside each gate structure. Multiple first spacers are formed on the sidewalls of each of the gate structure. Multiple second spacers are formed on the sidewalls of each of the isolation structure. A dielectric layer is formed on the substrate. Then, a self-aligned process is performed to form multiple contact openings in the dielectric layer between the gate structures. The conductive material is filled in the contact openings.Type: GrantFiled: September 21, 2005Date of Patent: November 3, 2009Assignee: Powerchip Semiconductor Corp.Inventors: Min-San Huang, Hann-Jye Hsu, Yung-Chung Yao
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Patent number: 7575027Abstract: A weave with a visual color variation, is interlaced by a plurality of longitudinal yarns and a plurality of latitudinal yarns. One of the longitudinal yarns and latitudinal yarns includes at least one protruding yarn and two color yarns with different colors. The protruding yarn has a plurality of protruding portions presenting on the surface of the weave. The two color yarns are arranged beside the protruding yarn respectively, and the two color yarns have a plurality of color portions presenting on the surface of the weave respectively. If the weave is observed from different viewing angles, the color portions are interfered by the protruding portion to make the weave show various visual color variations.Type: GrantFiled: January 5, 2007Date of Patent: August 18, 2009Inventor: Min-San Huang
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Publication number: 20090202800Abstract: A article with color variable patterns comprises a carrier having one printed surface; a pattern layer disposed on the printed surface and including a plurality of color blocks fixed thereon to form at least one color patterns, each color block including a number of color areas with different colors; and a plurality of refraction lenses mounted on the pattern layer; wherein the refraction lens is transparent and includes a top end of a cross section which is formed in a semi-circle shape, and a centrally vertical height h of the refraction lens is more than a radius length r thereof.Type: ApplicationFiled: April 20, 2009Publication date: August 13, 2009Inventor: Min-San Huang
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Patent number: 7550372Abstract: A method of fabricating conductive lines is described. A substrate having a polysilicon layer thereon is provided. A mask layer having an opening that exposes the polysilicon layer is formed on the polysilicon layer. Then, spacers are formed on the sidewalls of the mask layer. Using the mask layer and the spacers as a mask, a portion of the polysilicon layer is removed until the substrate is exposed. After that, an insulating layer that completely fills the opening is formed over the substrate. The insulating layer has an etching selectivity different from the mask layer. Thereafter, the mask layer is removed to expose the polysilicon layer and then a metal silicide layer is formed on the upper surface of the polysilicon layer.Type: GrantFiled: August 29, 2005Date of Patent: June 23, 2009Assignee: Powerchip Semiconductor Corp.Inventors: Su-Yuan Chang, Min-San Huang, Hann-Jye Hsu
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Publication number: 20090123852Abstract: A hard-material object comprising a visional color-varying surface comprises a hard-material carrier and a pattern disposed on the surface of the hard-material carrier. The pattern comprises a plurality of multi-color pellets to compose a picture. Each of the multi-color pellets comprises the distinct coloring regions distinguishable by the eyes so that a viewer can obtain different color-varying visional feeling from the pattern when the hard-material carrier is resting and looked at from different view angles.Type: ApplicationFiled: November 13, 2007Publication date: May 14, 2009Inventor: Min San Huang
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Publication number: 20090123672Abstract: A soft-material object comprising a visional color-varying surface comprises a soft-material carrier capable of generating varying rucks and a pattern disposed on the surface of the soft-material carrier. The pattern comprises a plurality of multi-color lumps to compose a picture. Each of the multi-color lumps comprises the distinct coloring regions distinguishable by the eyes so that a viewer can obtain different color-varying visional feeling from the pattern when the soft-material carrier is resting and looked at from different view angles or when the soft-material forms varying rucks itself in fixed eye angle.Type: ApplicationFiled: November 13, 2007Publication date: May 14, 2009Inventor: Min San Huang
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Publication number: 20080163952Abstract: The present invention relates to a weave with a visual color variation, which is interlaced by a plurality of longitudinal yarns and a plurality of latitudinal yarns. One of the longitudinal yarns and latitudinal yarns includes at least one protruding yarn and two color yarns with different colors. The protruding yarn has a plurality of protruding portions presenting on the surface of the weave. The two color yarns are arranged beside the protruding yarn respectively, and the two color yarns have a plurality of color portions presenting on the surface of the weave respectively. If the weave is observed from different viewing angles, the color portions are interfered by the protruding portion to make the weave show various visual color variations.Type: ApplicationFiled: January 5, 2007Publication date: July 10, 2008Inventor: Min-San Huang
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Publication number: 20080153289Abstract: A method for manufacturing a semiconductor device is disclosed. The method is suitable for a substrate having a first conducting structure and a first dielectric layer, wherein the dielectric layer covers the first conductive structure. The method includes the steps of forming a second conductive structure over the substrate adjacent to the first conductive structure. Then, the size of the second conductive structure is reduced so that a top surface of the second conductive structure is relatively lower than that of the first conductive structure. Thereafter, a second dielectric layer is formed over the substrate to cover the first and the second conductive structure. A via is formed in the second dielectric layer to expose the top surface of the first conductive structure. Finally, a via plug is formed in the via.Type: ApplicationFiled: March 4, 2008Publication date: June 26, 2008Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Min-San Huang, Dah-Chuan Chen, Rex Young
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Publication number: 20080124497Abstract: A pattern with a color varying function includes a number of picture units attached on a surface of a carrier. Each of the picture units includes a colorized design displaying directly or indirectly on the surface of the carrier and a transparent spherical grain covering the colorized design. The transparent spherical grain is configured for refracting the colorized design so as to produce various visual effects observing from different viewing angles or changing position angles of the carrier.Type: ApplicationFiled: November 29, 2006Publication date: May 29, 2008Inventor: Min-San Huang
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Patent number: 7368373Abstract: A method for manufacturing a semiconductor device is disclosed suitable for a substrate having a first conducting structure and a first dielectric layer, wherein the dielectric layer covers the first conductive structure. The method includes the steps of forming a second conductive structure over the substrate adjacent to the first conductive structure. Then, the size of the second conductive structure is reduced so that a top surface of the second conductive structure is relatively lower than that of the first conductive structure. Thereafter, a second dielectric layer is formed over the substrate to cover the first and the second conductive structure. A via is formed in the second dielectric layer to expose the top surface of the first conductive structure. Finally, a via plug is formed in the via.Type: GrantFiled: August 29, 2005Date of Patent: May 6, 2008Assignee: Powerchip Semiconductor Corp.Inventors: Min-San Huang, Dah-Chuan Chen, Rex Young
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Publication number: 20080079102Abstract: A method for fabricating an image sensor structure is provided. The method of fabricating an image sensor structure includes providing a substrate. An image sensor interconnect structure is formed on the substrate. A patterned stop layer is formed on the image sensor interconnect structure. An electrode layer, a first doped amorphous silicon layer and a first undoped amorphous silicon layer are conformably formed on the patterned stop layer and the image sensor interconnect structure not covered by the patterned stop layer in sequence. The first undoped amorphous silicon layer, the first doped amorphous silicon layer and the electrode layer are partially removed until the patterned stop layer is exposed by a planarization process, and each of a remaining electrode layer, a remaining first doped amorphous silicon layer and a remaining first undoped amorphous silicon layer are separated by the patterned stop layer.Type: ApplicationFiled: February 15, 2007Publication date: April 3, 2008Inventors: Yu-Hsien Chen, Min-San Huang, Chia-Chiang Wang
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Publication number: 20070202299Abstract: A pattern having variable colors can be attached on a soft material of wearing apparels or household cloths. The pattern is constituted of decorative blocks provided on the surface of the cloth or the soft material and a plurality of color-shielding pieces embedded on the surface of the decorative blocks. At least two opposite outer sides of the color-shielding piece are respectively provided with a colored block, so that the decorative blocks represent a visual effect of variable colors when viewed from different angles since the color-shielding pieces shield the colored blocks.Type: ApplicationFiled: August 21, 2006Publication date: August 30, 2007Inventor: Min-San Huang
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Publication number: 20070202300Abstract: A pattern having variable colors can be attached on a soft material of wearing apparels or household cloths. The pattern is constituted of decorative blocks provided on the surface of the cloth or the soft material and a layer of transparent film covering on the decorative blocks. The surface of the transparent film is formed with refractive ripples thereon, so that the decorative blocks represent a visual effect of variable colors by means of refraction when viewed from different angles.Type: ApplicationFiled: August 22, 2006Publication date: August 30, 2007Inventor: Min-San Huang
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Publication number: 20070158707Abstract: An image sensor including a substrate, a plurality of conductive sections, a first type doped layer, an intrinsic layer, and a transparent electrode layer is provided. Wherein, the conductive sections are disposed on the substrate, and the dielectric layer is disposed between two adjacent conductive sections. In addition, the first type doped layer overlays the conductive sections and the dielectric layer, and the intrinsic layer is disposed on the first type doped layer. Moreover, the transparent electrode layer is disposed on the intrinsic layer.Type: ApplicationFiled: March 29, 2006Publication date: July 12, 2007Inventors: Min-San Huang, Sian-Min Chung, Chia-Chiang Wang, Yu-Chun Lin, Wen-Tsung Chiu, Hung-Nien Chen
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Patent number: 7205217Abstract: A method for forming a trench gate dielectric layer is described. First, a substrate having a trench therein is provided. An in-situ steam generated oxidation process is performed to form a sacrificial layer on the surface of the trench. Then, the sacrificial layer is removed. Next, a low-pressure chemical vapor deposition is performed to form a gate dielectric layer on the surface of the trench.Type: GrantFiled: July 26, 2005Date of Patent: April 17, 2007Assignee: Powerchip Semiconductor Corp.Inventors: Min-San Huang, Hann-Jye Hsu, Liang-Chuan Lai
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Patent number: 7195982Abstract: A method for manufacturing an anti-punch through semiconductor device is described. The method is applied to a substrate having a plurality of device isolation structures in parallel arrangements and the upper surface of the device isolation structures is protruded from the surface of the substrate. A plurality of conductive layers in parallel arrangement is formed on the substrate and crosses the device isolation structures. A plurality of trench devices is formed between device isolation structures under the conductive layers. Each trench device includes a first conductive doping region at the bottom of the trench. The method further includes forming spacers on the sidewalls of the device isolation structures and the conductive layers. A dopant implant process is then performed by using the spacers as a mask to form a second conductive doping region between adjacent first conductive doping regions.Type: GrantFiled: May 10, 2005Date of Patent: March 27, 2007Assignee: Powerchip Semiconductor Corp.Inventors: Min-San Huang, Rex Young, Su-Yuan Chang