Abstract: A duty cycle correction circuit includes a duty correction circuit, an information generation circuit and a duty control circuit. The duty correction circuit corrects a duty rate of an input clock signal based on a duty control code to generate an output clock signal. The information generation circuit compares a difference between operation power voltages based on an operation mode to generate voltage information. The duty control circuit receives the voltage information from the information generation circuit and generates the duty control code that includes the voltage information based on a duty rate of the output clock signal.

Abstract: The present disclosure relates to a nanostructure for detecting viruses including an amphipathic polymer, and a diagnostic platform using the same, wherein the nanostructure is capable of specifically detecting viruses through silica-based nanoparticles with excellent stability and high dispersion and a biocompatible amphipathic polymer, such that it is possible to develop a diagnostic platform with high sensitivity through binding and agglomeration of the nanostructure and viruses and enable rapid and accurate diagnosis of a target virus.

Abstract: A method of operating an electronic system including a heterogeneous multi-core processor is provided. The method includes measuring the temperature and/or workload of a big (high-performance) core and switching a current core load from the big core to a small (low-power) core in response to the measured temperature and workload of the big core.

Abstract: There is provided a semiconductor package including: a semiconductor chip; and an extension die provided on the semiconductor chip, wherein the semiconductor chip includes a heating point configured to generate a temperature greater than or equal to a pre-determined reference temperature in the semiconductor chip, the heating point provided in a center region of the extension die

Abstract: A method of operating an electronic system including a heterogeneous multi-core processor is provided. The method includes measuring the temperature and/or workload of a big (high-performance) core and switching a current core load from the big core to a small (low-power) core in response to the measured temperature and workload of the big core.